Sr. Physical Design Engineer, Annapurna Labs

Job Title

Sr. Physical Design Engineer, Annapurna Labs

Role Summary

Design and optimize physical implementation of custom SoCs used in AWS machine learning servers (e.g., Inferentia, Trainium). Work within the Cloud-Scale Machine Learning Acceleration team to drive RTL-to-GDSII physical design closure, trade-offs for power-performance-area (PPA), and production sign-off.

Experience Level

Senior. Typical experience expectations in the posting: BS + 8 years or MS + 6 years in Electrical Engineering or Computer Science; 6+ years in ASIC physical design (RTL-to-GDSII).

Responsibilities

Primary responsibilities include delivering physical implementation and methodologies for complex SoC blocks and subsystems.

• Drive architectural feasibility studies and evaluate power-performance-area trade-offs with RTL/logic and architecture teams.
• Lead IO/core subsystem and block physical implementation: synthesis, floorplanning, bus/pin planning, place-and-route.
• Design and validate power/clock distribution networks; perform congestion analysis, timing closure, and IR drop analysis.
• Perform physical verification, equivalency checks, ECOs, and final sign-off activities.
• Develop and improve physical design methodologies and flows.
• Evaluate third-party IP for integration and recommend IP-related physical requirements.
• Collaborate closely with other physical design engineers and RTL/architecture teams to meet delivery and quality targets.

Requirements

Must-have technical skills and experience.

• Experience scripting in Python, Perl, Bash, or PowerShell.
• 6+ years of ASIC physical design experience (RTL-to-GDSII) using commercial EDA tools (examples: Cadence, Mentor Graphics, Synopsys, or similar).
• Hands-on experience with synthesis, equivalency verification, floorplanning, bus/pin planning, place-and-route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO processes.
• Deep understanding of sign-off activities: timing, IR/EM, and physical verification.

Nice-to-have / preferred:

• Experience mentoring, leading, or managing junior engineers.
• Expertise developing CAD tool flows and automation for physical design tasks.
• 4+ years integrating IP and defining IP requirements for physical implementation.
• Knowledge of device physics, custom/semi-custom implementation techniques, and experience with technologies such as DDR, PCIe, and fabrics.
• Experience extracting design parameters, quality-of-result (QOR) metrics, and performing trend analysis.

Education Requirements

Requires a Bachelor's degree plus 8 years' relevant experience, or a Master’s degree plus 6 years' relevant experience, in Electrical Engineering (EE) or Computer Science (CS). No alternative certifications or equivalent-experience language was specified in the posting.

About the Company

Company: KGS

KGS is a government and commercial contracting firm that provides engineering, technical, and staffing solutions, often supporting aerospace, defense, and IT projects for federal and industry customers.