Sr. Physical Design Engineer

Job Title

Sr. Physical Design Engineer

Role Summary

Contract senior physical-design consultant to architect and deliver RTL-to-GDS implementation and methodology for first-generation AI silicon. Two parallel roles: (1) Physical Design Methodology & Flow Consultant and (2) Physical Design Engineer (RTL-to-GDS).

Work cross-functionally with architecture, RTL, STA, DFT, power-integrity, verification, and signoff teams to create production-quality flows, automation, and implementation standards for a new chip program.

Experience Level

Senior - typically 15–20+ years of ASIC/SoC physical design, methodology, CAD, or implementation-flow experience.

Responsibilities

Deliver and operationalize the full-chip physical implementation flow and associated methodology; enable robust automation and cross-team integration.

• Architect, develop, deploy, and maintain the RTL-to-GDS physical-design flow for a new AI-silicon program.
• Define scalable methodologies for synthesis, floorplanning, placement, CTS, routing, optimization, extraction, STA, physical verification, and signoff.
• Lead implementation and optimization of Synopsys Fusion Compiler-based flows and related tool integrations.
• Create automation, scripts, configuration systems, checks, QoR reporting, and flow-health metrics.
• Support technology bring-up: libraries, PDK integration, corners, operating modes, constraints, and tool configuration.
• Develop multi-corner/multi-mode implementation and timing-closure methodologies.
• Partner with PD engineers to diagnose tool/flow/correlation/convergence issues and improve reproducibility, runtime, and scalability.
• Coordinate methodology and handoffs across synthesis, STA, DFT, power integrity, EMIR, PV, and full-chip integration.
• Document flows, train and mentor engineers, and evaluate new EDA capabilities for adoption or customization.

Requirements

Required skills and experience to perform the role; list separates must-have from desirable qualifications.

Must-have:

• 15–20+ years of ASIC/SoC physical-design, methodology, CAD, or implementation-flow experience.
• Proven experience developing RTL-to-GDS physical-design flows for complex, high-performance silicon.
• Demonstrated ability to define methodology for first-generation or ground-up chip programs rather than only maintaining mature flows.
• Deep knowledge of synthesis, floorplanning, place-and-route, clocking/CTS, STA, extraction, physical verification, and signoff.
• Full-chip and hierarchical implementation experience; expertise in multi-corner/multi-mode analysis and design closure.
• Strong scripting/automation skills (Tcl, Python, Perl, or equivalent) and experience building production-quality automation.
• Experience integrating EDA tools, standard-cell libraries, memories, IP, and design data into flows and diagnosing root causes across RTL, constraints, libraries, methodology, and tools.
• Experience working directly with front-end teams on physical-design-aware architecture and RTL co-design in an evolving R&D environment.

Nice-to-have:

• Expert-level experience with Synopsys Fusion Compiler; familiarity with Design Compiler, PrimeTime, IC Validator, RedHawk-SC, or similar tools.
• Experience with AI accelerators, GPUs, CPUs, networking silicon, advanced process nodes, very large hierarchical designs, HBM, packaging/chiplets, or high-performance interconnects.
• Experience using AI-assisted EDA, flow-health dashboards, automated regression systems, and QoR tracking.

Education Requirements

Not specified.

About the Company

Company: VeriFast Technologies

VeriFast Technologies is an engineering consulting firm specializing in advanced semiconductor physical design, methodology, and EDA tool integration for high-performance ASIC/SoC programs, including AI accelerators and first-generation silicon projects.