Sr. Member Technical Staff - ESD and Latch-Up - HBM

Job Title

Sr. Member Technical Staff - ESD and Latch-Up - HBM

Role Summary

Define and deliver ESD and latch-up protection architecture for next-generation HBM products across base die, DRAM stacks, TSVs, and advanced packaging. Work with device, circuit, packaging, foundry, and validation teams to translate system-level reliability requirements into design and signoff criteria.

Experience Level

Senior level — requires extensive industry experience. The posting specifies 10+ years of experience in ESD and latch-up design and reliability.

Responsibilities

The role owns end-to-end ESD and latch-up strategies and drives technical decisions from architecture through silicon validation.

• Define end-to-end ESD and latch-up architecture across base die, DRAM die, and interconnects.
• Develop protection strategies for high-speed I/O, TSV interfaces, and advanced packaging.
• Establish ESD/latch-up standards, rule decks, and signoff criteria for product release.
• Drive correlation between design assumptions, silicon validation results, and field reliability data.
• Partner with foundry, packaging, and cross-functional teams to resolve system-level ESD issues.
• Provide technical leadership and influence product reliability direction early in the design cycle.
• Mentor engineers and contribute to PDK and rule-deck development where required.

Requirements

Key must-have and preferred technical qualifications and skills.

• Must-have: 10+ years of experience in ESD and latch-up design and reliability.
• Must-have: Expertise in advanced CMOS technologies such as FinFET or GAA.
• Must-have: Practical experience with 3D IC, TSV, or die-to-die interfaces and system-level protection strategies.
• Must-have: Demonstrated ability to define protection strategies for high-speed I/O and advanced packaging and to drive correlation between design and silicon validation.
• Nice-to-have: Experience defining architecture across multi-die or stacked memory systems (HBM).
• Nice-to-have: Background in ESD device or circuit design and experience developing PDK collateral or ESD rule decks.
• Nice-to-have: Experience debugging silicon failures related to ESD or latch-up and demonstrated cross-functional technical leadership.

Education Requirements

MS or PhD in Electrical Engineering or a related field, or equivalent practical experience.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.