Sr. Layout Engineer

Job Title

Sr. Layout Engineer

Role Summary

Design and develop mask layouts for next-generation low-voltage (LV) and medium-voltage (MV) shielded-gate trench MOSFET technologies. Work closely with process integration teams and external foundry partners to optimize device performance and accelerate industrialization.

Role is part of the manufacturing/layout team based in Takasaki and contributes to mask specification, verification, and tapeout documentation.

Experience Level

Senior level. The posting references at least 5+ years of relevant mask layout experience and indicates a preference for candidates with 10+ years.

Responsibilities

Primary responsibilities include mask layout design, verification, and tapeout coordination:

• Perform chip layout design for LV/MV shielded-gate trench MOSFETs following design manuals and rules (Cadence Virtuoso or equivalent).
• Run and verify mask design rule checks (e.g., Mentor Calibre or equivalent).
• Define and document mask specifications such as pellicle and inspection requirements.
• Design scribe areas and accessory layouts including alignment and inspection marks.
• Prepare tapeout-related documentation, shot maps, and provenance tracking.
• Coordinate schedules and activities with process integration engineers and external foundry partners.

Requirements

Must-have skills and experience; preferred items listed where applicable.

• Must-have: Significant experience in mask layout design for power semiconductor devices (explicitly listed as 5+ years; preference indicated for 10+ years).
• Must-have: Hands-on experience with chip layout tools and layout verification tools (e.g., Cadence Virtuoso, Calibre).
• Must-have: Experience defining mask specifications and producing tapeout deliverables (pellicle, inspection spec, shot maps, scribe design).
• Must-have: Ability to coordinate with product and process engineers and with external foundries to drive industrialization.
• Must-have: Communication skills in both English and Japanese at business/conversational levels (English ~daily conversation; Japanese business conversation).
• Nice-to-have: Direct experience with LV/MV shielded-gate trench MOSFET technologies.

Education Requirements

Not specified.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.