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SR Engineer, ASIC DFT

Micron Technology
June 08, 2026
Full-time
On-site
Hyderabad, Telangana, India
DFT Jobs, Level - Senior

Job Title

Senior Engineer, ASIC DFT

Role Summary

Implement and validate design-for-test (DFT) solutions for Micron ASICs and SoCs, focusing on scan, memory BIST/repair, logic BIST and ATPG to ensure testability and low defect rates. Work closely with RTL design, verification, physical implementation, test engineering and product teams to support silicon bring-up and characterization.

Experience Level

Senior β€” typically requires 5+ years of industry experience in ASIC/SoC DFT or related roles.

Responsibilities

Primary responsibilities include implementing DFT features, validating test patterns, and collaborating with multi-functional teams to support silicon bring-up and methodology development.

  • Implement and validate DFT (Scan, MBIST, LBIST, boundary scan) at RTL and gate level for hard macros and chip-top.
  • Generate and validate ATPG patterns and perform fault simulation.
  • Perform SDF-annotated gate-level verification and scan/memory diagnosis.
  • Collaborate with STA, synthesis, LEC, CLP, verification, physical implementation and test engineering teams.
  • Support silicon bring-up activities to ensure stability and quality of test patterns/programs.
  • Contribute to the development and improvement of DFT methodology.

Requirements

Must-have technical skills and tool experience.

  • Minimum 5+ years of industry experience in DFT for complex SoCs.
  • Experience with Scan Codec insertion, Memory BIST and repair, Logic BIST, ATPG, BSCAN & JTAG (IEEE 1149.1 & IEEE 1687), and ATPG fault models (SAF, TDF, SDD, PDT).
  • Experience in fault simulation, ATPG pattern generation, SDF-annotated gate-level verification, and scan/memory diagnosis.
  • Proficiency with Siemens, Synopsys and/or Cadence EDA tools.
  • Experience coding in Verilog or VHDL and scripting/programming in C/C++, TCL, Perl and/or Python.

Nice-to-have:

  • Knowledge of IEEE 1149.6, 1500 and 1838; hierarchical scan and core wrapping techniques.
  • Experience with multi-clock domains, low-power DFT techniques, SSN, or 2.5D/3D IC DFT implementations.
  • Experience collaborating across geographies and time zones; strong time-management skills.

Education Requirements

Bachelor's or Master's degree (or equivalent practical experience) in Electronics Engineering, Microelectronics, Software Engineering or a related technical field.


About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.

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Date Posted: 2026-06-08