Sr Digital Design Engineer

Job Title

Sr Digital Design Engineer

Role Summary

Senior engineer responsible for front-end RTL design and implementation of advanced DRAM digital and mixed-signal blocks. Deliver RTL-to-GDS quality by working with architecture, verification, and physical design teams to meet product specifications and PPA (Power, Performance, Area) goals.

Experience Level

Senior — typically requires 4+ years post-Master's or 5+ years post-Bachelor's experience in digital ASIC/RTL design as indicated in the minimum qualifications.

Responsibilities

Primary responsibilities include front-end RTL development, timing and power optimization, and improving design flows.

• Design, develop, and deliver RTL for complex DRAM digital and mixed-signal blocks from specification through implementation handoff.
• Perform front-end quality checks: linting, CDC/RDC analysis, functional verification support, and static timing analysis.
• Create and maintain synthesis and timing constraints (SDC); analyze timing reports and drive timing closure across multi-mode multi-corner scenarios.
• Collaborate with architecture, verification, and physical design teams to optimize power, performance, and area (PPA).
• Apply low‑power design methodologies and UPF-based power intent to meet power targets.
• Improve RTL-to-GDS flows, tooling, and automation to increase development efficiency and design quality.

Requirements

Must-have technical skills and experience.

• Proven experience developing RTL for complex digital designs through implementation handoff.
• Strong knowledge of front-end ASIC design flows: RTL design, logic synthesis, CDC/RDC analysis, and static timing analysis (STA).
• Experience developing and maintaining SDC including clocks, timing exceptions, I/O constraints, and multi-mode multi-corner timing scenarios.
• Proficiency with Verilog/SystemVerilog and industry-standard simulation tools.
• Experience with timing closure, analyzing timing reports, and driving fixes across teams.
• Experience with low-power design methodologies, UPF-based power intent, and PPA optimization.

Nice-to-have:

• Experience with memory product RTL or other high-performance digital designs.
• Familiarity with CMOS digital and mixed-signal circuit concepts.
• Experience improving engineering productivity via automation and process improvements.
• Experience collaborating across architecture, verification, and physical implementation teams; strong communication and problem-solving skills.
• Familiarity with AI-assisted tools to improve engineering efficiency is a plus.

Education Requirements

Master's degree in Electrical Engineering (or equivalent) with 4+ years of relevant experience, or Bachelor's degree with 5+ years of relevant experience in digital ASIC/RTL design; equivalent practical experience is acceptable per the posting.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.