Sr DFT Engineer

Job Title

Sr DFT Engineer

Role Summary

The Sr DFT Engineer will design and implement design-for-test (DFT) features for subsystem blocks of Mythic's SoC, owning MBIST, iJTAG, scan, ATPG and related flows. The role focuses on establishing DFT methodology and flows to enable first-pass silicon success and requires cross-team collaboration with RTL, physical design, STA and analog teams.

Experience Level

Senior. The posting requests at least 3+ years of industry experience.

Responsibilities

Primary responsibilities include implementing DFT features, integrating them at SoC level, and enabling successful silicon bring-up.

• Implement MBIST, IEEE 1687 (iJTAG), JTAG (1149.x), scan insertion and ATPG for subsystem blocks.
• Integrate DFT at SoC level and manage hierarchical DFT strategies.
• Develop and document DFT methodology and flows to achieve first-pass silicon success.
• Define and execute pre-silicon test plans and verification strategies.
• Collaborate with RTL, physical design, STA, analog, and ATE teams to define timing constraints, resolve issues, and support bring-up.
• Perform root-cause analysis and debug DFT implementation and yield issues.
• Contribute across the design cycle from concept through silicon.

Requirements

Must-have and preferred technical skills and experience.

• Must-have: Minimum 3+ years industry experience in DFT; hands-on experience with SoC-level DFT integration, verification, and RTL design for DFT.
• Solid understanding of DFT methodologies: JTAG (1149.x), IEEE 1500, IEEE 1687 (iJTAG), scan, ATPG, memory BIST.
• Experience with scan insertion, test point insertion (TPI), SSN, hierarchical DFT and ATPG strategies.
• Experience in pre-silicon test planning and verification strategies.
• Proficiency in Verilog/SystemVerilog and DFT toolflows (e.g., Synopsys TetraMAX/DFT Compiler or Mentor/Siemens Tessent).
• Good scripting skills (Perl, Tcl, Python, or similar) and strong communication skills for a distributed team.
• Nice-to-have: Low-power DFT solutions, ATE bring-up and yield-debug experience, prior AI-processor design experience, chiplet design awareness, Sub-10nm experience, familiarity with Cadence toolsets.

Education Requirements

BS, MS, or PhD in Electrical Engineering / Electronics Engineering / Computer Engineering (BS/MS/PhD in EE/ECE as stated). The posting does not explicitly state whether equivalent practical experience is accepted.

About the Company

Company: Mythic

Headquarters: Austin, Texas, USA

Mythic is revolutionizing AI computing through innovative analog technology, significantly enhancing performance compared to traditional digital systems. Their cutting-edge solutions cater to demanding applications in various sectors, including industrial, automotive, and aerospace. With over $100M raised from top investors, Mythic is poised to transform AI workloads and applications.