Sr. Design for Test (DFT) Engineer

Job Title

Sr. Design for Test (DFT) Engineer

Role Summary

Responsible for Design-for-Test insertion, ATPG, and post-silicon DFT bring-up for production ASICs used in AI acceleration systems. Work spans synthesis through place-and-route, timing closure, and tape-out signoff.

Collaborate closely with RTL, physical-design, and ATE teams to ensure testability and support silicon validation.

Experience Level

Senior — minimum 5 years industry DFT experience with at least 2 completed tapeouts.

Responsibilities

Primary responsibilities include test insertion, pattern generation, and bringing tests to silicon and ATE.

• Perform DFT insertion: internal scan, boundary scan, and memory BIST.
• Run automatic and targeted test pattern generation (ATPG).
• Support post-silicon DFT bring-up and debug of test programs.
• Interface with Physical Design and RTL teams to assess DFT impact on timing, power, and layout.
• Collaborate with ATE engineers for test program bring-up and debugging.
• Develop scripts and automation for DFT and ATPG flows (Python, TCL, or similar).
• Participate in tape-out signoff and drive issues to closure.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• Must-have: Minimum 5 years industry experience as a DFT engineer on ASIC designs.
• Must-have: At least 2 completed tapeouts.
• Must-have: Minimum 2 years experience with standard DFT CAD tools and flows.
• Must-have: Hands-on scripting experience (Python, TCL, or similar) and automation of DFT/ATPG flows.
• Must-have: Experience with DFT/post-silicon/ATPG in both ASIC and semi-custom COT flows.
• Must-have: Experience supporting post-silicon bring-up and interfacing with ATE engineers for test program debug.
• Strong teamwork and cross-functional collaboration skills; ability to adapt in a fast-paced environment.
• Ability to comply with applicable U.S. export control laws.
• Nice-to-have: Multiple production-quality ASIC tapeouts beyond the minimum.
• Nice-to-have: Experience with ATE test program development and fault modeling.
• Nice-to-have: Understanding of timing, physical design, and power impact of DFT structures; familiarity with SoC architecture and HDLs such as SystemVerilog.

Education Requirements

Required: Bachelor's degree in Electrical Engineering or a related field. Preferred: Master's degree in Electrical Engineering (mentioned as preferred in the posting). The posting allows related technical fields; no specific certifications were listed.

About the Company

Company: Lightmatter

Headquarters: Boston, Massachusetts, USA

Lightmatter develops photonic AI data-center infrastructure and optical chips for extreme-scale AI and HPC. The company invented the Passage 3D‑stacked photonics engine to provide high-bandwidth, low-latency interconnects across large-scale processors and raised $400M in Series D financing at a reported $4.4B valuation.