Sr. ASIC & FPGA Verification Engineer

Job Title

Sr. ASIC & FPGA Verification Engineer

Role Summary

Responsible for developing and executing verification environments and tests for ASIC and FPGA designs. Implements UVM/SystemVerilog testbenches, writes assertions and functional coverage, and performs RTL debug to validate design behavior.

Onsite role supporting sensitive work that requires U.S. citizenship and eligibility for a government security investigation.

Experience Level

Senior — typically 10+ years of ASIC and FPGA verification experience with strong UVM/SystemVerilog expertise.

Responsibilities

Core responsibilities include:

• Design, implement, and debug UVM/SystemVerilog testbench components (environments, configuration, agents, drivers, monitors, sequencers, sequences, base tests)
• Create directed and constrained-random tests, assertions, and functional coverage
• Perform RTL debug using the UVM/SV testbench to isolate and resolve design issues
• Integrate verification components into regression frameworks and analyze results
• Collaborate with RTL designers to identify and close verification gaps

Requirements

Must-have and preferred qualifications:

• Must-have: 10+ years of ASIC and FPGA verification experience; UVM/SystemVerilog expertise
• Must-have: Demonstrated RTL debug experience within UVM/SV testbench environments
• Must-have: U.S. citizenship and ability to pass a U.S. Government security investigation for access to classified information
• Nice-to-have: Experience with Mentor verification tools
• Nice-to-have: Experience developing functional coverage plans and integrating verification into regression systems

Education Requirements

Not specified.

About the Company

Company: CxDesign

Engineering consulting and staffing firm recruiting for ASIC and FPGA verification and embedded systems roles.