Sr. ASIC DFT Engineer (Silicon)

Job Title

Senior ASIC DFT Engineer (Silicon)

Role Summary

Work on Design-for-Test (DFT) for next-generation ASICs used in the Starlink system. You will implement and verify on-chip test architectures, support ATPG and compression flows, and enable post-silicon bringup and production testability.

Collaborate with cross-functional teams (design, validation, firmware, manufacturing) to ensure chips meet test and production requirements.

Experience Level

Senior. The posting specifies 5+ years of experience in semiconductor DFT engineering, post-silicon validation, and/or production testing.

Responsibilities

The role focuses on DFT architecture implementation, ATPG flows, silicon bringup, and automation.

• Design and optimize DFT architectures: scan insertion, compression/decompression logic, memory BIST, and logic BIST.
• Integrate and verify DFT IPs and fabrics within subsystem designs.
• Set up and run ATPG tools and methodologies for stuck-at, transition, and path-delay fault models; focus on pattern compression, diagnosis, and hierarchical test flows.
• Run and debug non-timing and SDF-annotated gate-level simulations for test validation.
• Create and validate DFT patterns for post-silicon bringup and support ATE debug during silicon characterization cycles.
• Develop test scripts, automate processes, and analyze test data using Perl, Python, Tcl, or C++.

Requirements

Must-have skills and constraints for consideration; preferred items are listed separately.

• 5+ years of hands-on semiconductor DFT, post-silicon validation, and/or production test experience.
• Experience with ATPG workflows, pattern compression, and diagnosis techniques.
• Practical experience with Siemens Tessent tool flows or equivalent DFT toolchains.
• Post-silicon bringup and silicon debug experience (creating patterns for bringup and supporting ATE debug).
• Scripting and automation skills (Perl, Python, Tcl, or C++).
• Ability to work extended hours and weekends as needed to meet critical milestones.
• ITAR eligibility: must meet U.S. Government export-regulation eligibility (U.S. citizen, lawful permanent resident, refugee, asylee, or otherwise eligible to obtain required authorizations).

Education Requirements

Required: Bachelor's degree in Electrical Engineering, Computer Engineering, or Physics. Preferred: Master’s or PhD in Electrical Engineering, Computer Engineering, Physics, or a related engineering field. (Degrees explicitly listed in the posting.)

Preferred Skills

Nice-to-have skills that strengthen candidacy.

• Advanced degree (Master’s or PhD) in a related technical field.
• Extensive experience with post-silicon bringup, failure analysis, and yield optimization on complex SoCs/ASICs.
• Hands-on experience with ATE platforms (Teradyne, Advantest) for high-volume test development and debug.
• Knowledge of industry testability standards (e.g., IEEE 1500, IEEE 1687) and low-power DFT techniques.
• Experience with In-System Test (IST), boundary-scan (IEEE 1149.1), board-level diagnostics, or Tessent Streaming Scan Network.
• Familiarity with cell-aware fault models in ATPG and working at advanced nodes (e.g., 7 nm and below).
• Strong problem-solving and communication skills for documenting strategies and presenting results to stakeholders.

Additional Information

SpaceX is an equal opportunity employer. Applicants requiring reasonable accommodation for the application or interview process may contact EEOCompliance@spacex.com.

About the Company

Company: SpaceX

Headquarters: Hawthorne, California, United States

SpaceX is focused on developing space technologies to enable human exploration of Mars and beyond. The company is known for its advancements in rocketry and its Starlink satellite constellation, which delivers high-speed internet globally.