Sr. ASIC Design Engineer (Silicon Engineering)

Job Title

Sr. ASIC Design Engineer (Silicon Engineering)

Role Summary

Develop RTL and deliver synthesis- and timing-clean ASICs for the Starlink system, working across systems, firmware, architecture, verification, and physical implementation teams. The role focuses on micro-architecture, RTL implementation in Verilog/SystemVerilog, verification cooperation, and silicon bring-up for space and ground hardware.

Experience Level

Senior - requires experienced engineers; posting specifies 5+ years of relevant RTL implementation experience.

Responsibilities

Core responsibilities include designing, implementing, and validating RTL and supporting flow handoffs to verification and physical implementation.

• Evaluate architectural trade-offs based on features, performance, and system constraints.
• Define micro-architecture and implement RTL using Verilog/SystemVerilog; integrate into top-level designs.
• Deliver fully verified, synthesis- and timing-clean designs compatible with physical implementation.
• Collaborate closely with verification teams to ensure coverage of design functionality.
• Provide timing constraints and support synthesis, timing closure, and formality checks with the physical implementation team.
• Participate in silicon bring-up and validation activities.

Requirements

Must-have technical skills and constraints, plus preferred skills.

• Must-have: 5+ years of RTL implementation experience and strong Verilog/SystemVerilog skills.
• Must-have: Experience creating timing constraints and supporting synthesis/timing closure for IPs.
• Must-have: Experience with silicon bring-up and hardware validation.
• Must-have: Ability to work extended hours or weekends as needed for mission-critical deadlines.
• Must-have: Must meet U.S. ITAR eligibility (U.S. citizen, lawful permanent resident, refugee, or asylee) - U.S. person requirement for this role.
• Nice-to-have: Experience with clock-domain crossing and power-optimization techniques.
• Nice-to-have: ASIC/SoC integration experience and familiarity with embedded CPU subsystems.
• Nice-to-have: Familiarity with standard bus protocols (AXI, AHB) and high-speed or low-power design techniques.
• Nice-to-have: Scripting skills (Python) and experience with EDA tools (HDL simulators, lint tools).
• Nice-to-have: Strong teamwork, communication, and a learning-oriented mindset.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science (specified as a basic qualification in the posting).

About the Company

Company: SpaceX

Headquarters: Hawthorne, California, United States

SpaceX is focused on developing space technologies to enable human exploration of Mars and beyond. The company is known for its advancements in rocketry and its Starlink satellite constellation, which delivers high-speed internet globally.