Sort Interface Pathfinding and Development Engineer

Job Title

Sort Interface Pathfinding and Development Engineer

Role Summary

Join Intel's Advanced Packaging, Test and Manufacturing organization to develop and qualify electro-mechanical probing and test hardware for wafer and die sort across advanced packaging platforms (EMIB, Foveros, etc.).

The role leads pathfinding, supplier co-design, and probe/process qualification to enable internal and external Foundry/OSAT test flows and new product introductions.

Experience Level

Mid-level (experienced hire). The posting expects multiple years of industry experience (see Requirements for details).

Responsibilities

Deliver technical leadership for sort interface pathfinding and supplier readiness.

• Design and execute Design of Experiments (DOE) to optimize probing technologies and contact architectures for wafer and die sort.
• Act as technical liaison to Foundry and OSAT customers, translating chiplet/package requirements into scalable sort interface specifications.
• Author sort design rules and Interface Design Kits (IDKs) to support ecosystem integration.
• Collaborate with customer design and DFT teams to define test interface hardware and resolve testability gaps.
• Partner with test solution vendors and PCB/substrate suppliers to develop probing capabilities and align roadmaps.
• Lead supplier management, pathfinding initiatives, and manufacturing readiness to meet NPI schedules.

Requirements

Must-have technical experience and capabilities required for initial consideration. Education degree specifics are listed under Education Requirements.

• Must-have: Several years of industry experience with wafer/die sort technology, prober-tester cell integration, or qualification of advanced probe card technologies.
• Must-have: Experience structuring and executing DOEs to evaluate probing margins, yield, and process health.
• Must-have: Direct experience with ATE test hardware/methodology, Sort/Class product development, or PCB/space-transformer/substrate design rules and stackups.
• Nice-to-have: Experience qualifying probe technologies for fine-pitch micro-bumps, 2.5D/3D architectures (EMIB, silicon bridges), or wafer-level chip-scale probing.
• Nice-to-have: Hands-on experience with commercial ATE platforms such as Advantest V93k or Teradyne Ultra-FLEX.
• Soft skills: Strong cross-functional collaboration, technical communication, analytical problem solving, customer focus, and ability to drive projects with minimal supervision.

Education Requirements

Bachelor's degree in Electrical Engineering, Mechanical Engineering, Materials Science, or a related STEM field with 6+ years' industry experience; OR Master's degree in those fields with 4+ years' industry experience; OR Ph.D. in those fields with 2+ years' relevant post-graduate or industry experience. Equivalent practical experience is acceptable as described in the minimum qualifications.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.