SoC Verification Technical Lead / Senior Staff

Job Title

SoC Verification Technical Lead / Senior Staff

Role Summary

Lead and execute SoC, subsystem, and IP verification engagements for Synopsys customers, from verification planning through signoff. Work with customer engineering teams to define scope, deliverables, and verification strategy.

Manage small verification teams, mentor engineers, and drive methodology and tooling improvements to reduce cycle time and improve coverage quality.

Experience Level

Senior — 8+ years of hands-on SoC, subsystem, or IP verification experience (as specified in the posting).

Responsibilities

Accountabilities for this role include technical leadership, delivery, and continuous improvement of verification processes and results.

• Lead verification execution for customer SoC, subsystem, and IP projects from planning through signoff.
• Build and manage verification teams (typically 3–8 engineers); assign tasks, review testbenches and coverage, and mentor engineers through debug.
• Develop verification plans mapping requirements to testbench architecture, coverage goals, and resource allocation; track execution and adjust as designs evolve.
• Integrate and deploy Synopsys VCS, Verdi, and third-party VIP for protocols such as PCIe, Ethernet, USB, and DDR into customer environments.
• Debug complex multi-protocol and multi-domain SoC issues using waveform and coverage analysis and cross-functional collaboration.
• Identify project risks early, propose mitigations, and communicate status and blockers to Synopsys management and customer stakeholders.
• Drive verification methodology improvements (UVM reuse, regression optimization, new tool adoption) across the team.

Requirements

Must-have technical skills and proven track record of delivering SoC verification projects.

• Deep expertise in UVM testbench development, coverage analysis, verification planning, and multi-domain debug.
• Proven experience leading verification teams through full project cycles, including resource planning and delivery against customer schedules.
• Strong working knowledge of industry-standard protocols (PCIe, Ethernet, USB, DDR) and their interaction in SoC architectures.
• Hands-on proficiency with Synopsys VCS and Verdi or equivalent waveform/coverage tools; experience integrating third-party VIP into verification environments.
• Solid understanding of ASIC design flows, RTL concepts, and how verification fits into chip development.
• Excellent customer-facing communication and ability to translate architecture-level descriptions into verification risk assessments and plans.
• Nice-to-have: Experience with ARM-based technologies (Coresight, AMBA), post-silicon debug exposure, or experience on 5nm and below flows.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Computer Engineering, or a related field (as stated in the posting).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.