SOC Verification Senior Engineer

Job Title

SOC Verification Senior Engineer

Role Summary

Senior verification engineer responsible for defining and executing verification strategies for processor-based SoCs. Work within the Systems Solutions Group to build test plans, develop SystemVerilog/UVM testbenches, debug multi-clock-domain simulation failures, and collaborate with architects, RTL designers, and silicon validation teams.

The role is customer-facing and focuses on shipping real customer SoCs and subsystems across domains such as HPC, automotive, aerospace, and defense.

Experience Level

Senior — the title indicates a senior-level role. The posting requests 2 to 5 years of hands-on IP or SoC verification experience.

Responsibilities

Primary responsibilities include planning, implementation, and debugging of SoC verification efforts.

• Build verification test plans from design specs, define scope, coverage goals, and realistic test scenarios.
• Develop and maintain SystemVerilog testbenches and UVM environments; integrate Synopsys and third-party VIPs.
• Write and analyze SystemVerilog assertions and manage code, toggle, and functional coverage to close verification gaps.
• Debug complex simulation failures across multi-clock-domain SOC designs using VCS and waveform viewers; isolate root causes.
• Mentor and guide junior verification engineers during design bring-up, testbench architecture decisions, and debugging.
• Collaborate with architects, RTL designers, and post-silicon teams to align verification strategy with design and validation plans.
• Automate regression and verification flows using shell, Makefile, Perl, and scripting to improve efficiency and reproducibility.

Requirements

Essential technical skills and practical experience required for the role. Degree information is summarized separately under Education Requirements.

• Strong working knowledge of SystemVerilog and UVM in processor-based SoC verification environments.
• Experience with VCS, waveform debugging tools, and integrating third-party verification IP into testbenches.
• Solid understanding of AXI and AMBA protocol variants, including corner-case and error-condition behavior.
• Proficiency scripting automation flows and regression infrastructure using shell, Makefile, or Perl.
• Working knowledge of ASIC design flow and RTL design concepts and how verification fits into the chip development lifecycle.
• Ability to debug across clock domains and interpret waveforms, logs, and coverage metrics to close verification gaps.
• Good communication and mentoring skills to lead debugging sessions and code reviews.
• Nice-to-have: experience with ARM core verification and protocols such as USB, PCIe, or MIPI.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering or a related field. The posting specifies 2–5 years of hands-on IP or SoC verification experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.