SoC Verification - Senior Engineer

Job Title

SoC Verification - Senior Engineer

Role Summary

Senior verification engineer on the Systems Solutions Group delivering verification for processor-based SoCs and subsystems. Responsible for defining verification scope and coverage, implementing SystemVerilog/UVM testbenches, integrating VIPs, and debugging complex multi-clock-domain issues to prevent silicon respins.

This is a customer-facing role working on real customer SOCs across markets such as HPC, automotive, and aerospace, collaborating with architects, RTL designers, and post-silicon teams.

Experience Level

Senior. Experience guidance: 2–5 years of hands-on IP or SOC verification experience (as listed by the employer).

Responsibilities

Key responsibilities include:

• Create verification test plans from design specs, set coverage goals, and map tests to real-world scenarios.
• Develop and maintain SystemVerilog testbenches and UVM environments; integrate Synopsys and third-party VIPs for protocols such as AXI, USB, PCIe, and MIPI.
• Write and analyze SystemVerilog assertions and manage code, toggle, and functional coverage to close verification gaps before tapeout.
• Debug complex simulation failures across multi-clock-domain SOCs using VCS, waveform viewers, and scripting to isolate root causes.
• Mentor junior verification engineers on testbench architecture, bring-up, and debugging practices.
• Collaborate with architects, RTL designers, and silicon validation teams to align verification strategy with design intent and post-silicon plans.
• Automate regression and verification flows using shell, Makefile, and Perl to improve efficiency and reusability.

Requirements

Must-have technical skills and experience.

• Strong working knowledge of SystemVerilog and UVM for verification environment development.
• Experience with VCS and waveform debugging tools to diagnose simulation failures.
• Experience integrating verification IP (VIP) into testbenches.
• Solid understanding of AXI/AMBA protocol behaviors, corner cases, and error conditions.
• Proficiency in scripting to automate regressions and post-process results (shell, Makefile, Perl).
• Working knowledge of ASIC design flow and RTL design concepts.

Nice-to-have:

• Experience with ARM core verification and protocol-specific verification for USB, PCIe, or MIPI.
• Familiarity with Synopsys VIP and other third-party verification IP.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering or a related field. The posting specifies 2–5 years of hands-on IP or SoC verification experience; no alternative "equivalent experience" language was provided.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.