SoC Verification — Principal Engineer

Job Title

SoC Verification — Principal Engineer

Role Summary

Lead verification planning and execution for customer SoC, subsystem, and IP projects within the System Solutions Group (SSG). Work directly with customer engineering teams to define scope, deliverables, and verification signoff.

The role includes hands-on debug, testbench and coverage strategy, VIP integration, and mentoring a small team of verification engineers to deliver production-quality silicon.

Experience Level

Senior — requires 12+ years of hands-on SoC, subsystem, or IP verification experience as stated in the posting.

Responsibilities

Accountable for verification delivery, technical leadership, and customer engagement.

• Lead verification execution from planning through signoff for customer SoC/subsystem/IP projects.
• Manage and mentor verification teams (typically 3–4 engineers): assign tasks, review testbenches and coverage, and guide complex debug.
• Create verification plans mapping requirements to testbench architecture, coverage goals, and resource allocation; track and adjust execution.
• Integrate and deploy Synopsys VCS, Verdi, and third-party VIP for protocols (PCIe, Ethernet, USB, DDR) into verification environments.
• Debug complex multi-protocol and multi-domain SoC issues using waveform and coverage analysis and collaborate with design, architecture, and post-silicon teams.
• Identify project risks early, propose mitigations, and communicate status to Synopsys management and customer stakeholders.
• Drive verification methodology improvements: UVM reuse, regression optimization, and new tooling adoption.

Requirements

Must-have technical skills and demonstrated experience for immediate contribution.

• Deep expertise in UVM testbench development, coverage analysis, and verification planning.
• Proven track record leading verification teams through full project cycles, including delivery to customer schedules.
• Strong working knowledge of protocols (PCIe, Ethernet, USB, DDR) and their interaction in SoC architectures.
• Hands-on proficiency with Synopsys VCS and Verdi or equivalent waveform analysis tools; experience integrating third-party VIP.
• Skilled at multi-domain SoC debug and root-cause analysis across power, interconnect, and accelerator blocks.
• Working understanding of ASIC design flows and RTL concepts and how verification integrates with chip development.
• Experience mentoring engineers and providing clear, actionable technical feedback.
• ARM-based technologies (Coresight, processor architecture, AMBA) considered a strong plus.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Computer Engineering, or a related field is specified. The posting also specifies 12+ years of hands-on SoC/subsystem/IP verification experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.