SoC Verification Architect — Digital (SystemVerilog / UVM)
Lead the digital verification architecture and strategy for SoC projects at STMicroelectronics Italia in Naples. The role focuses on defining verification approaches, building UVM/SystemVerilog testbenches, and coordinating verification activities across design, firmware and validation teams.
Senior — typically 5–8 years of experience in digital verification. The title "Architect" implies senior responsibility for verification strategy and technical leadership.
Primary responsibilities include defining verification architecture and delivering robust verification environments for SoC digital blocks.
Must-have skills and experience for successful performance in this role.
Bachelor's degree in Electronic/Electrical Engineering or a related technical field (laurea in Ingegneria Elettronica). Equivalent practical experience is acceptable.
Company: STMicroelectronics
Headquarters: Geneva, Switzerland
Global semiconductor company that designs, develops and manufactures a broad range of semiconductor integrated circuits and discrete devices for automotive, industrial, personal electronics and communications markets. Offers microcontrollers, sensors, power management, analog and mixed-signal solutions and related software and services.
