SoC Verification Architect – Digital (SystemVerilog / UVM)

Job Title

SoC Verification Architect 6 Digital (SystemVerilog / UVM)

Role Summary

Lead the functional verification of digital SoC blocks and subsystems. Work within the verification team to design and implement SystemVerilog/UVM environments, define verification plans, and ensure coverage closure at block and integration levels.

Collaborate with RTL designers, architects and integration teams to identify issues early, drive root-cause analysis, and deliver validated verification deliverables.

Experience Level

Senior-level. Approximately 5 68 years of experience in digital verification, ideally with SoC-level projects.

Responsibilities

Key responsibilities include:

• Design and develop SystemVerilog/UVM verification environments and testbenches for digital IP and SoC blocks.
• Create and run constrained-random and directed tests; implement functional coverage and assertions.
• Define and execute verification plans; track coverage and drive closure to sign-off criteria.
• Debug functional issues at block and subsystem level; perform root-cause analysis with RTL teams.
• Integrate verification components for subsystem/SoC-level validation and support integration testing.
• Mentor and review work from junior verification engineers; contribute to process and methodology improvements.

Requirements

Must-have and preferred qualifications.

• Must-have: 5 68 years of hands-on digital verification experience, including strong practical knowledge of SystemVerilog and UVM.
• Must-have: Proficiency in scripting/programming with C and Python for testbench and automation tasks.
• Must-have: Experience with SoC or complex IP verification, testbench development, functional coverage, and assertion-based verification.
• Must-have: Proven debugging skills and experience collaborating with RTL designers on issue resolution.
• Nice-to-have: Experience with emulation, FPGA prototyping, formal verification, or advanced verification tools and flows.
• Nice-to-have: Prior leadership of verification efforts or architecture-level verification responsibilities.

Education Requirements

Bachelor's degree in Electronic/Electrical Engineering (Ingegneria Elettronica) or a related technical field is indicated in the source. Higher technical degrees in similar fields are acceptable.

About the Company

Company: STMicroelectronics

Headquarters: Geneva, Switzerland

Global semiconductor company that designs, develops and manufactures a broad range of semiconductor integrated circuits and discrete devices for automotive, industrial, personal electronics and communications markets. Offers microcontrollers, sensors, power management, analog and mixed-signal solutions and related software and services.