SOC Top-Level Physical Design Engineer, Annapurna Labs

Job Title

SOC Top-Level Physical Design Engineer, Annapurna Labs

Role Summary

Design and optimize SoC physical implementation for AWS custom accelerators (Inferentia, Trainium) including full-chip floorplanning, placement, integration, physical verification (PV) signoff and tapeout. Work on cloud-scale ML server hardware within the Cloud-Scale Machine Learning Acceleration team and collaborate with front-end, layout, and foundry partners.

Los Angeles County applicants: this role includes duties that require safe, cooperative work, sound judgment, and adherence to company policies. Pursuant to the Los Angeles County Fair Chance Ordinance, qualified applicants with arrest and conviction records will be considered.

Experience Level

Senior - this role expects substantial industry experience. Candidates should have significant hands-on experience in physical verification and advanced-node chip integration (typical expectation: multiple years in PV and backend flows; see Requirements for specifics).

Responsibilities

Primary responsibilities focus on end-to-end physical integration, verification, and collaboration across design and foundry teams.

• Drive full-chip floorplan, placement, integration, physical verification signoff, and tapeout.
• Collaborate with front-end teams to influence physical aspects early in the design cycle.
• Define, execute, and optimize physical verification and integration methodologies using industry EDA tools.
• Perform DRC, LVS, and PERC verification; debug and resolve PV issues with layout and design teams.
• Interface with foundries for rule deck updates, waiver processes, and MT form handling.
• Develop and maintain verification runsets, flows, and automation for PV closure.
• Mentor junior engineers on physical verification methodologies and closure strategies.

Requirements

Must-have technical skills and experience needed to perform the role.

Must-have:

• Hands-on scripting experience (Python, Perl, Bash, or PowerShell).
• 5+ years of experience in physical verification for advanced technology nodes.
• Understanding of backend physical design flows for chip-top and subsystems (e.g., Fusion Compiler / Innovus).
• Expertise with industry-standard PV tools (Calibre, IC Validator, PVS).
• Strong knowledge of semiconductor manufacturing processes and design rules.
• Proven track record of successful tape-outs.
• Effective written and verbal communication; ability to collaborate across teams.

Nice-to-have:

• Experience mentoring, leading, or managing junior engineers.
• Experience with integration and verification at advanced nodes (5nm or below).
• Familiarity with custom and digital design flows and DFM methodologies.
• Expertise in reliability verification (ESD, EM, IR drop) and extraction/QoR analysis.
• Experience addressing physical-design challenges for interfaces and fabrics (DDR, PCIe, fabrics).

Education Requirements

BS + 10 years, or MS + 7 years in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field (as listed in the posting).

About the Company

Company: Amazon

Headquarters: Seattle, Washington, United States

Amazon is a global leader in e-commerce and cloud computing, committed to delivering fast, reliable services across diverse sectors. The company's innovative technologies include AWS, Kindle, and Echo, as well as developing low Earth orbit satellite networks for improved internet connectivity worldwide.