SOC Timing Engineer

Job Title

SOC Timing Engineer

Role Summary

Responsible for static timing analysis (STA), timing closure and signoff for FPGA/SoC and subsystem designs. Works with design, architecture, and physical design teams to achieve timing convergence and final timing signoff.

Experience Level

Mid-level; requires approximately 3+ years of experience in physical design, timing closure and signoff.

Responsibilities

Key responsibilities include:

• Perform static timing analysis and timing signoff for SoC/FPGA and subsystems.
• Derive and provide interface timing constraints to design partitions.
• Collaborate with design and architecture teams for timing convergence analysis.
• Work with physical design teams to achieve timing closure across PVT corners.
• Support tapeout readiness and resolve timing-related issues during signoff.

Requirements

Must-have:

• Experience with industry STA tools such as Synopsys PrimeTime / PTPX.
• Strong understanding of timing constraints, clocking strategies and PVT variations.
• Tapeout experience at advanced nodes (10 nm or smaller).
• Proven experience in physical design and timing closure/signoff (3+ years recommended).
• Strong communication, problem-solving and analytical skills.

Nice-to-have:

• Experience with FPGA/SoC subsystem timing and interface constraint derivation.

Education Requirements

Bachelor's (BE), Master's (MS) or PhD in Electronics / Electrical Engineering (as stated in the posting).

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.