SoC Static Timing Analysis (STA) Engineer, HBM

Job Title

SoC Static Timing Analysis (STA) Engineer, HBM

Role Summary

As an STA Engineer in the Heterogeneous Integration Group (HIG), you will own chip-level timing sign-off for next-generation HBM die. You will partner with RTL, physical design, architecture, DFT, verification, and product teams to ensure timing integrity from initial design through tape-out.

Experience Level

Senior-level; requires 10+ years of hands-on chip-level STA and multiple tape-outs at 5nm or below.

Responsibilities

Primary responsibilities include timing sign-off, constraint development, and automation:

• Own end-to-end chip-level static timing analysis and sign-off across checks, modes, corners, voltages, and temperatures.
• Develop, validate, and maintain sign-off quality Synopsys Design Constraints (SDC) for clocks, resets, HBM interfaces, DFT, and configuration logic.
• Drive timing closure at block, subsystem, and full-chip levels via critical path analysis, ECOs, and collaboration with physical design on placement, CTS, and routing.
• Perform multi-mode, multi-corner analysis including CDC timing, OCV/AOCV/POCV, and advanced-node timing methodologies.
• Lead signal integrity and crosstalk analysis and partner with physical design teams on mitigation strategies.
• Build and maintain STA automation and flows using Python and Tcl for reporting, regression tracking, and sign-off readiness.
• Conduct post-silicon timing correlation and define organization-wide STA methods, sign-off standards, and readiness reviews.
• Mentor junior engineers and clearly communicate timing status, risks, and closure plans to cross-functional teams and senior management.

Requirements

Must-have qualifications and preferred skills:

• Must-have: 10+ years of hands-on experience owning chip-level STA and full timing sign-off on multiple tape-outs at 5nm or below.
• Must-have: Deep experience with Synopsys PrimeTime and/or Cadence Tempus.
• Must-have: Expert understanding of multi-mode multi-corner analysis, on-chip variation, signal integrity, and power-aware timing.
• Must-have: Proven ability to develop and manage complex hierarchical SDC constraints for large SoCs with multiple clock and power domains.
• Must-have: Proficiency in Python and/or Tcl for timing flow automation, constraint management, and quality-of-results reporting.
• Preferred: Experience with HBM, DRAM, or memory-centric SoC designs.
• Preferred: Exposure to DFT timing (scan, MBIST, JTAG) and chiplet/3D IC timing methodologies.
• Preferred: Familiarity with foundry PDKs, Liberty timing models, and advanced noise/variation modeling.
• Preferred: Strong communication skills and willingness to work with or learn agentic AI to help develop efficient workflows.

Education Requirements

Not specified.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.