SoC Static Timing Analysis (STA) Engineer, HBM

Job Title

SoC Static Timing Analysis (STA) Engineer, HBM

Role Summary

As a SoC STA Engineer in the Heterogeneous Integration Group, you will own chip-level static timing analysis and sign-off for next-generation HBM products from initial design through tape-out. You will work with RTL, physical design, architecture, DFT, verification, and product teams to ensure timing integrity and drive closure across modes and corners.

The role includes developing timing methodology, constraint authoring, automation, post-silicon correlation, and integrating AI-enabled tools into STA workflows.

Experience Level

Senior — 15+ years of hands-on STA experience, including multiple tape-outs at advanced nodes (5nm or below).

Responsibilities

Key responsibilities include ownership of chip-level STA, methodology and automation development, and cross-team coordination.

• Own end-to-end static timing analysis and sign-off across all checks, modes, corners, voltages, and temperatures.
• Develop, maintain, and validate sign-off quality Synopsys Design Constraints (SDC) for clocks, resets, HBM interfaces, DFT, and configuration logic.
• Drive timing closure through critical path analysis, ECOs, and collaboration with physical design on placement, clock tree synthesis, and routing.
• Perform multi-mode multi-corner (MMMC) analysis including CDC timing, on-chip variation (OCV/AOCV/POCV), and power-aware timing methods.
• Lead signal integrity and crosstalk analysis and coordinate mitigation strategies with physical design teams.
• Build and maintain STA automation and flows using Python and Tcl for reporting, regression tracking, and sign-off readiness.
• Conduct post-silicon timing correlation and define sign-off standards, readiness reviews, and tape-out sign-off gates.
• Integrate and enable AI-driven tools and workflows to improve timing closure and methodology.

Requirements

Must-have skills and experience:

• 15+ years owning chip-level STA and full timing sign-off on multiple tape-outs at 5nm or below.
• Deep expertise with Synopsys PrimeTime and/or Cadence Tempus.
• Expert understanding of multi-mode multi-corner analysis, on-chip variation, signal integrity, and power-aware timing.
• Proven ability to develop and manage complex hierarchical SDC constraints for large SoCs with multiple clock and power domains.
• Proficiency in Python and/or Tcl for timing flow automation and quality-of-results reporting.
• Nice-to-have: experience with HBM/DRAM interfaces, DFT timing (scan, MBIST, JTAG), chiplet or 3D IC timing methodologies.

Education Requirements

Not specified.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.