SoC STA/Timing Engineer (Staff / Senior Staff)

Job Title

SoC STA/Timing Engineer - Staff / Senior Staff

Role Summary

Work on static timing analysis (STA) setup, convergence, validation, and signoff for multi-mode, multi-voltage SoC and subsystem designs. Deliver timing closure, automate STA/PD flows, and support ECO timing fixes across the backend implementation flow.

The role partners with design, DFT, synthesis, technology, CAD and physical implementation teams to ensure timing correctness across PVT corners and low-power domains.

Experience Level

Senior / Staff level. Typical requirement: approximately 7–15 years of relevant STA/ASIC backend experience focused on timing signoff and convergence.

Responsibilities

Key responsibilities for this role include:

• Perform STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain SoC and subsystem designs.
• Validate and debug timing across multiple PVT corners using industry STA tools.
• Run and correlate STA flows with transistor-level (Spice) results where applicable.
• Develop and optimize timing methodologies; automate STA and physical design flows with scripting.
• Drive ECO timing flows and logical equivalence checks from RTL to netlist.
• Collaborate with design, DFT, synthesis, technology, CAD and implementation teams to resolve timing issues.
• Mentor junior engineers on timing flows, constraints, and signoff practices.
• Apply low-power timing techniques including clock gating, power gating, and multi-voltage domain handling.

Requirements

Must-have technical skills and experience:

• Strong STA fundamentals, including AOCV/POCV, CTS, and timing constraints formulation.
• Hands-on experience with STA tools such as PrimeTime and Tempus.
• Familiarity with backend physical implementation tools (ICC2, Innovus) and ASIC flows.
• Scripting proficiency in TCL, Perl, and Python for flow automation.
• Understanding of signal integrity, cross-talk, and parasitic extraction and their impact on timing.
• Experience with ECO timing flows and RTL-to-netlist equivalence checks.
• Experience interpreting and correlating Spice simulations (Hspice, FineSim, Monte Carlo) with STA results.

Nice-to-have:

• Experience driving timing convergence at chip-level and hard-macro level.
• Exposure to full RTL-to-GDSII flows.
• Strong technical writing and cross-team communication skills.

Education Requirements

Bachelor's, Master's or PhD in Computer Science, Electrical/Electronics Engineering, Engineering or a related field. The posting specifies degree-dependent experience: Bachelor's +6+ years, Master's +5+ years, or PhD +4+ years of Hardware Engineering or related work experience.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.