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SoC RTL Design - Staff Engineer

Qualcomm
September 04, 2026
Full-time
On-site
Chennai, Tamil Nadu, India
RTL Design Jobs, Level - Senior

Job Title

SoC RTL Design - Staff Engineer

Role Summary

Senior RTL/SoC front-end engineer responsible for designing, coding, integrating and closing timing for complex SoC blocks. The role works within the hardware engineering/ASIC front-end team and interfaces with verification, validation, and physical design teams to deliver production-quality RTL for SoC integration.

Experience Level

Senior. Preferred 10–15 years of digital front-end ASIC/RTL design experience; minimum experience may vary with degree (see Education Requirements).

Responsibilities

Core responsibilities include RTL design, SoC integration, timing closure, and collaboration across verification and physical design teams.

  • Design and implement logic/micro-architecture in Verilog/SystemVerilog for SoC subsystems.
  • Integrate IP and subsystems into SoC-level RTL and collaborate on chip-level integration.
  • Develop constraints and drive timing closure; work with synthesis and timing tools.
  • Implement and validate low-power design techniques for SoC designs.
  • Design and verify multi-clock and asynchronous interfaces; address CDC and related issues.
  • Support pre- and post-silicon debug with verification and validation teams.
  • Coordinate with floorplanning and pad-ring teams when required for chip-level deliverables.

Requirements

Must-have technical skills and practical experience.

  • Hands-on RTL coding and micro-architecture experience in Verilog/SystemVerilog.
  • Proven SoC design and integration experience, including understanding of SoC clocking, reset, and debug architecture.
  • Practical experience with AMBA protocols (AXI, AHB, APB) and common on-chip peripherals (e.g., USB, PCIe, SDCC).
  • Experience with synthesis and timing concepts for ASIC flows; familiarity with constraint development and timing closure.
  • Experience with multi-clock designs and asynchronous interfacing; familiarity with CDC analysis and mitigation.
  • Hands-on use of ASIC front-end and signoff tools such as Lint tools, CDC tools, Design Compiler, and PrimeTime.
  • Must have hands-on low-power SoC design experience.
  • (Nice-to-have) Understanding of memory controller designs and microprocessor interfaces.
  • (Nice-to-have) Experience creating pad rings and working with chip-level floorplan teams.

Education Requirements

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related engineering field (with 2+ years hardware engineering experience), OR Master's degree in those fields (with 1+ year of hardware engineering experience), OR PhD in Computer Science, Electrical/Electronics Engineering, or a related engineering field.


About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.

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Date Posted: 2026-09-03