SoC RTL Design Engineer, Senior Staff

Job Title

SoC RTL Design Engineer, Senior Staff

Role Summary

Senior RTL design and signoff engineer in the System Solutions Group responsible for RTL quality signoff, static verification, synthesis validation, formal equivalence, and IP integration for production SoC projects.

Work spans IP blocks, subsystems, and full SoC builds to reduce respin risk and enable tapeout for customers in AI, automotive, 5G, and IoT domains.

Experience Level

Senior — requires 8+ years of hands-on RTL design and verification experience.

Responsibilities

Primary responsibilities include:

• Run RTL quality signoff using Spyglass (LINT, CDC, RDC) across IP, subsystems, and SoC designs.
• Develop SDC timing constraints for synthesis and static timing analysis to reflect design intent and architecture.
• Execute preliminary synthesis runs (Design Compiler or Fusion Compiler) to validate synthesizability, area, and timing feasibility.
• Perform RTL-to-gate formal equivalence checking using Formality for design revisions and ECOs.
• Integrate third-party and Synopsys IP into customer SoCs, resolving clocking, reset, and interface protocol issues.
• Create or modify RTL blocks to meet customer requirements and delivery timelines within established design guidelines.
• Collaborate with verification, implementation, and architecture teams to close signoff issues before tapeout.

Requirements

Must-have technical skills and experience:

• Proven experience performing static verification using Spyglass or equivalent (LINT, CDC, RDC) on complex digital designs.
• Working knowledge of synthesis tools such as Design Compiler or Fusion Compiler, including constraint development and synthesis quality checks.
• Hands-on experience with Formality or equivalent formal verification tools for RTL-to-gate equivalence checking.
• Solid conceptual understanding of clock domain crossing, reset domain crossing, metastability, and common design pitfalls.
• Experience integrating IP blocks into subsystems or SoCs and resolving interface, clocking, and protocol issues.
• Ability to analyze static-check reports and prioritize true issues versus tool noise; effective communication in design reviews.
• Nice-to-have: Familiarity with scripting in Tcl, Python, or Perl to automate checks, reporting, and flows.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or Computer Engineering. The role specifies 8+ years of hands-on RTL design and verification experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.