SoC RTL Design Engineer

Job Title

SoC RTL Design Engineer

Role Summary

Integrate and prepare RTL for SoC and subsystem implementation and verification. Work across IP designers, architects, verification, physical design, DFT, firmware, and methodology teams to ensure RTL quality, synthesis readiness, and successful handoff to downstream implementation.

Experience Level

Mid-level. Typical hire requires approximately 3+ years of relevant RTL, SoC integration, synthesis, or ASIC/FPGA experience.

Responsibilities

Primary responsibilities include front-end integration, quality checks, and preparing designs for synthesis and implementation.

• Integrate RTL from multiple IPs, subsystems, and reusable components into top-level SoC and subsystem designs.
• Develop and maintain top-level RTL wrappers, hierarchy, interconnect, clock/reset structures, interrupts, and configuration logic.
• Work with standard SoC protocols and interfaces (AXI, AHB, APB, memory, debug, interrupt, clock, reset, power-management).
• Coordinate IP releases, manifests, parameters, build configurations, and design collateral.
• Run and debug RTL compile/elaboration, lint, CDC/RDC, structural checks, formal connectivity, and synthesis flows.
• Prepare RTL, constraints, libraries, and configuration inputs for synthesis and downstream physical implementation.
• Analyze synthesis reports for timing, area, power, high-fanout, unmapped logic, and DRC issues; collaborate with physical design to resolve timing and congestion risks.
• Support functional equivalence, gate-level simulation, emulation, FPGA, ECO, and design-release readiness activities.
• Investigate failures across RTL, tools, constraints, and build environments; identify root cause and drive corrective actions.
• Participate in design, code, and integration reviews; contribute to methodology improvements and technical documentation.

Requirements

Must-have technical skills and experience; preferred items noted separately.

• 3+ years of relevant work experience in RTL design, SoC integration, synthesis, ASIC/FPGA development, or equivalent.
• Practical experience with Verilog or SystemVerilog and hierarchical RTL integration.
• Experience with RTL simulation, compilation/elaboration, lint, CDC/RDC, and synthesis/front-end flows.
• Understanding of digital design fundamentals, timing concepts, clock/reset design, bus protocols, and hardware/software interfaces.
• Ability to analyze technical problems, communicate root cause, and work in distributed cross-functional teams.

Education Requirements

Minimum: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. Preferred: Master's degree in the same areas. The posting accepts related technical fields; equivalent practical experience may be considered where appropriate.

Preferred Qualifications

Nice-to-have skills that improve effectiveness in the role.

• Experience integrating complex SoCs, subsystems, NoC/interconnect, memory, debug, security, or power-management logic.
• Hands-on work with synthesis, timing constraints, timing analysis, area/power optimization, formal equivalence, ECO, or gate-level simulation.
• Experience with low-power design concepts (power intent, isolation, retention, multi-voltage), CDC/CDC crossing techniques, and reset-domain crossings.
• Scripting skills (Python, Perl, Tcl, Shell) for flow automation, quality checks, reporting, and build management.
• Familiarity with commercial or internal EDA tools for simulation, linting, CDC, synthesis, formal verification, and implementation handoff.
• Experience with SoC release QA, connectivity signoff, and reusable IP/subsystem delivery processes.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.