SoC Principal Physical Design Engineer
SynopsysJob Title
SoC Principal Physical Design Engineer
Role Summary
Lead physical implementation and methodology for advanced-node SoC designs from RTL through GDSII tapeout. Work with internal teams and external semiconductor customers to define and execute floorplanning, power, placement, CTS, routing, and signoff strategies that meet PPA targets on 5nm, 3nm and below.
Experience Level
Senior - 10–15+ years of hands-on ASIC/SoC physical design experience with multiple advanced-node tapeouts.
Responsibilities
Primary responsibilities focus on technical leadership of physical implementation, customer enablement, and automation to accelerate timing closure and improve PPA.
- Lead full-chip and block-level physical implementation from RTL through GDSII on advanced-node designs (5nm, 3nm, below).
- Define and execute floorplanning, power planning, placement, clock tree synthesis, routing, and signoff strategies.
- Drive timing closure, power optimization, congestion reduction, and area improvement using Fusion Compiler and PrimeTime.
- Perform and review static timing analysis, ECO implementation, IR-drop analysis, electromigration checks, and physical verification with IC Validator.
- Work directly with customers to troubleshoot design challenges, deliver technical workshops, and provide methodology guidance.
- Develop automation and flows using Python, Tcl, Perl, and shell scripting to improve productivity.
- Leverage AI/ML-based physical design technologies and tool optimizations to accelerate closure and explore design tradeoffs.
Requirements
Must-have technical skills and hands-on experience for immediate contribution.
- 10–15+ years of hands-on ASIC/SoC physical design experience with multiple successful tapeouts at advanced nodes.
- Deep expertise in floorplanning, power planning, placement & routing, clock tree synthesis, timing closure, and physical verification (DRC/LVS).
- Strong working knowledge of IR-drop analysis, electromigration analysis, and ECO methodologies for late-stage fixes.
- Proficiency with scripting for automation (Python, Tcl, Perl, shell).
- Practical experience with Synopsys tools such as Fusion Compiler, PrimeTime, IC Validator, StarRC, Formality; PrimePower and StarRC experience is a plus.
- Familiarity with foundry process technologies (TSMC, Samsung, Intel) and advanced-node design considerations.
- Proven customer-facing skills, technical leadership, and ability to mentor junior engineers.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
