SoC Power Design Engineer (Staff Engineer)

Job Title

SoC Power Design Engineer (Staff Engineer)

Role Summary

Implement and validate SoC-level low-power design intent and power projections. Collaborate with frontend RTL, DFT, synthesis, verification and physical design teams to deliver power models, UPF-based intent, and validated power budgets from pre-silicon through post-silicon.

Experience Level

Senior (Staff level). Typical experience guidance from minimum qualifications: ~4+ years with a bachelor's, 3+ with a master's, or 2+ with a PhD.

Responsibilities

Primary responsibilities include:

• Implement and validate SoC-level power intent (UPF) and ensure IP compliance with SoC power requirements.
• Collaborate with RTL, DFT, synthesis, verification, and physical design teams to integrate low-power features.
• Generate and validate power intent design at SoC level and review IP power features and budgets/estimates.
• Perform power analysis and projection of SoC baseline power; deliver power models and dashboards.
• Improve power design flows, tools, and power modeling; work with CAD groups and vendors to enhance flows.
• Track IP power development through the design cycle and validate leakage/dynamic budgets at milestones.
• Execute power-aware implementation flows and run power simulations/analysis (e.g., PtPx, PowerArtist, Prime Power, PowerPro).

Requirements

Must-have technical skills:

• ASIC frontend development and SoC-level low-power implementation experience.
• Logic design, RTL coding, verification, synthesis, and timing closure.
• Hardware description languages: Verilog, VHDL, SystemVerilog.
• Power-aware implementation flow experience: UPF/CPF and Conformal Low Power Check.
• Scripting: Perl, Tcl, Python.
• Experience with power analysis and projection tools (PtPx, PowerArtist, Prime Power, PowerPro).

Nice-to-have:

• Familiarity with overall SoC infrastructure: DDR, buses, CPUs, I/Os, and DFT components.
• Experience with power islands, power gating, power sequencing, and multi-voltage domain design.
• Knowledge of clock-tree power, peak power/TDP and limits management.
• Experience collaborating with CAD teams, vendors, and post-silicon test teams.

Education Requirements

Bachelor's degree in Science, Engineering, or related field (plus ~4+ years experience), or Master's degree in Science, Engineering, or related field (plus ~3+ years), or PhD in Science, Engineering, or related field (plus ~2+ years). Preferred fields: Electrical Engineering or Computer Engineering; a master's is noted as preferred.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.