SoC Power Architecture Engineer - Processor Subsystem

Job Title

SoC Power Architecture Engineer - Processor Subsystem

Role Summary

Design and implement power-domain architectures for ASIC-based processor subsystems used in satellite IoT devices. The role partners with SoC architects, physical design, and verification teams to deliver low-power partitioning, control sequencing, and UPF power intent for energy-constrained systems.

Primary focus is on aggressive duty cycling, ultra-low standby power, retention strategies, and fast wake-up latency for satellite link windows.

Experience Level

Senior — 7+ years of ASIC/SoC design experience with a strong focus on low-power architecture.

Responsibilities

Own the power-domain definition and ensure correct implementation and verification across RTL and physical flows.

• Define and architect always-on, switchable, and retention power domains for processor subsystems.
• Partition subsystems including embedded processors, interconnects, and peripherals for low-power operation.
• Develop power-sequencing state machines and control logic to meet fast wake-up and low-power constraints.
• Specify and integrate isolation cells, level shifters, power switches, and retention registers.
• Capture and review power intent using UPF (IEEE 1801) and ensure consistency with RTL.
• Collaborate with physical design for power-aware synthesis, place-and-route, and sign-off flows.
• Engage with verification teams to validate power-domain behaviors across sleep and deep-sleep modes.
• Adapt reference processor subsystem designs to meet satellite IoT energy and duty-cycle requirements.

Requirements

Required technical skills and hands-on experience.

• 7+ years of ASIC/SoC design experience with a focus on low-power architecture.
• Deep, hands-on experience defining power domains, isolation strategies, and retention architectures.
• Proficiency with UPF (IEEE 1801) power intent format and power intent workflows.
• Strong RTL design experience using SystemVerilog or VHDL.
• Proven experience optimizing for ultra-low power in energy-constrained applications (IoT, wearables, etc.).
• Familiarity with low-power synthesis and physical-design constraints affecting power architecture.

Nice-to-have:

• Experience with Arm Corstone or similar processor subsystem IP (e.g., Cortex-M series).
• Knowledge of AMBA bus protocols (AHB, APB, AXI) and power-domain crossings.
• Experience with power analysis tools (e.g., Synopsys PrimeTime PX, Cadence Joules).
• Understanding of battery-powered and energy-harvesting constraints and PMIC interfaces.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field (as stated in the posting).

About the Company

Company: E-Space

Headquarters: Saratoga, CA, United States

E-Space develops low Earth orbit (LEO) satellite systems to enable hyper-scaled Internet of Things (IoT) connectivity. The company designs advanced satellite hardware and communication systems to reduce costs, improve scalability, and deliver actionable intelligence from space.