SoC Power Analysis Engineer

Role Summary

The SoC Power Analysis Engineer focuses on analyzing power consumption of SoCs (System on Chips) across a variety of use cases, identifying optimization opportunities, and generating power optimal recipes to assist design teams in creating efficient designs at various levels, including architecture and RTL.

Experience Level

This role requires a proficient engineer with over 7 years of experience in power analysis and PTPX flows, as well as expertise in implementing power optimal designs at the physical design stage.

Responsibilities

The key responsibilities for this position include:

• Collaborating with architects, hardware, and firmware engineers to optimize designs based on use cases and implemented power features.
• Building test plan documentation for subsets of use case tests.
• Working with simulation teams to obtain necessary fsdb files for power analysis and design optimization.
• Running PTPX to generate power metrics, analyzing consumption, and correlating power data with previous project benchmarks.
• Identifying methods to implement power optimal designs and sharing strategies with physical design teams.

Requirements

The ideal candidate will have the following qualifications:

• Strong proficiency in Power analysis and PTPX flows with a minimum of 7 years of experience.
• Experience in implementing power optimal designs during the Physical design stage.
• Knowledge of physical design flows such as ICC, Fusion Compiler, or Innovus.
• Familiarity with battery life workloads and related analyses, along with test definition for power use cases.
• Proficiency in programming languages including Verilog, System Verilog, C, and C++.
• Experience using fsdbs, VCS simulation, and formality endpoint mapping.
• Knowledge of scripting languages such as Perl and Python.

Education Requirements

A Bachelor's or Master's degree in Computer Engineering or Electrical Engineering is required.