SoC Physical Design Engineer (Senior to Principal)
QualcommJob Title
SoC Physical Design Engineer (Senior to Principal)
Role Summary
Deliver technical leadership for block- and chip-level physical implementation of advanced FinFET SoCs. Own backend physical design methodology, floorplanning and place-and-route execution, and drive automation of the PD flow.
The role champions integration of Agentic AI into PD flows, mentors engineers, and coordinates with foundry, EDA vendors, and senior stakeholders to achieve tape-out readiness.
Experience Level
Senior to Principal. Typical experience guidance varies by degree (see Education Requirements) - generally mid-to-senior level engineers with multiple years of ASIC physical design and chip implementation experience.
Responsibilities
Primary responsibilities include hands-on physical implementation, flow ownership, and technical leadership.
- Define and implement block- and full-chip floorplanning, place-and-route, ECOs, and timing/power closure strategies.
- Develop, maintain, and optimize RTL-to-GDS backend flows and automation frameworks.
- Perform STA, power analysis, physical verification, and complex design simulations for PPA optimization.
- Lead implementation of advanced design rules and processes; evaluate synthesis, P&R, timing, power, and verification signoff paths.
- Document and review technical designs, trade-offs, and tape-out readiness reports for senior management.
- Mentor and provide technical guidance to team members; interface with foundry and EDA vendors.
Requirements
Must-have technical skills and experience for this role; degree details are listed under Education Requirements.
- Proven ASIC/SoC physical design experience: floorplanning, P&R, ECO, STA, timing and power closure, and physical verification.
- Strong scripting and automation skills (advanced Shell, Python, Tcl); ability to architect large-scale back-end automation frameworks.
- Practical experience with timing closure methodologies (LEC, static timing analysis) and power signoff flows.
- Experience with power optimization techniques (DVFS, multi-Vt, power domains) and familiarity with UPF/CPF is desirable.
- Ability to lead technical decisions, present risk assessments, and communicate readiness to senior stakeholders.
- Experience working with foundries and EDA vendors; ability to influence cross-functional implementation choices.
- Demonstrated ability to work independently and provide guidance to other engineers.
- Nice-to-have: demonstrated experience or vision for applying Agentic AI/LLM-assisted tools to EDA challenges and autonomous optimization.
Education Requirements
Bachelor's, Master's, or PhD in Computer Science, Electrical/Electronics Engineering, Computer Engineering, VLSI, Physics, or a related technical field; equivalent practical experience is acceptable. The posting describes degree-specific experience expectations (examples): Bachelor's +4–6+ years, Master's +3–5+ years, PhD +2–4+ years depending on role seniority.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
