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Senior Engineer - IC Design (RTL AMS)

Silicon Labs
September 29, 2026
Full-time
On-site
Hyderabad, Telangana, India
RTL Design Jobs, Level - Senior

Job Title

Senior Engineer - IC Design (RTL AMS)

Role Summary

Develop, integrate, and verify digital RTL blocks for mixed-signal IPs and subsystems. Work with analog designers, system architects, verification engineers, and SoC teams to deliver synthesis-ready, low-power, functionally robust IP for integration into complex SoCs.

Experience Level

Senior level. The posting indicates approximately 3+ years of experience in digital RTL design with mixed-signal exposure.

Responsibilities

Deliver and validate digital RTL for mixed-signal IPs and support integration into SoCs.

  • Develop synthesizable RTL for mixed-signal IPs (ADC/DAC interfaces, PLL/DLL control, PMU, sensor front-ends).
  • Define and implement digital–analog interface logic and communication protocols in collaboration with analog teams.
  • Create behavioral models, run simulations, and perform co-verification with analog components.
  • Perform lint, CDC/RDC checks, and prepare designs for synthesis.
  • Participate in design and micro-architecture reviews; document IP functionality and timing interfaces.
  • Integrate IPs into SoC top-level RTL and debug functional or timing issues during full-chip validation.
  • Work with verification engineers to define test plans, drive coverage closure, and debug cross-domain issues.
  • Contribute to automation, methodology improvements, and reuse strategies for mixed-signal IP development.

Requirements

Core technical skills and experience required or strongly preferred.

  • Must-have: Proficiency in Verilog/SystemVerilog and experience with synthesis and static verification flows (lint, CDC).
  • Must-have: Practical experience in digital RTL design and integration with mixed-signal subsystems.
  • Must-have: Familiarity with digital communication protocols (SPI, I2C, APB, AXI) and clocking/sampling concepts relevant to mixed-signal designs.
  • Must-have: Scripting experience for design flow automation (Python, TCL, Perl).
  • Nice-to-have: Hands-on experience with mixed-signal co-simulation tools (Cadence AMS Designer, Synopsys VCS AMS, etc.).
  • Nice-to-have: Prior work on SoC integration, power-management logic, or sensor interfaces.
  • Ability to work in cross-functional teams and communicate design and verification issues effectively.
  • Experience using AI-powered tools to improve productivity and analysis is a plus.

Education Requirements

B.E./B.Tech or M.S./M.Tech in Electrical Engineering, Electronics, Computer Engineering, or a closely related field.

Company Summary

Silicon Labs is a semiconductor company focused on low-power wireless connectivity and highly integrated SoCs used in smart home, industrial IoT, and smart cities applications.

Benefits

  • Equity rewards (RSUs)
  • Insurance plans with outpatient cover
  • National Pension Scheme (NPS)
  • Flexible work policy and childcare support

About the Company

Company: Silicon Labs

Headquarters: Austin, Texas, USA

Silicon Labs is a leading innovator in low-power wireless connectivity, creating embedded technology that connects devices to improve lives. With a focus on advanced edge connectivity applications, the company provides device makers with cutting-edge solutions and support. Headquartered in Austin, Texas, Silicon Labs operates in over 16 countries, serving markets such as smart home, industrial IoT, and smart cities.

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Date Posted: 2026-09-28