SoC Physical Design Engineer (Senior to Principal)
QualcommJob Title
SoC Physical Design Engineer (Senior to Principal)
Role Summary
Senior-level physical design engineer responsible for block-, die-, and chip-level physical implementation on advanced FinFET nodes. The role owns backend design methodology, drives automation, and delivers high-quality, low-power SoC implementations.
The engineer will provide technical leadership, mentor other engineers, and collaborate with cross-functional teams, foundries, and EDA vendors to achieve timing, power and physical verification goals.
Experience Level
Senior to Principal level. Typical minimum experience indicated is roughly 3–4+ years of ASIC/hardware physical design (requirements vary by degree); higher-level roles expect significantly more experience.
Responsibilities
Deliver and lead physical implementation activities across IP blocks and full chips.
- Define and execute floorplanning, place-and-route, ECO, STA, timing and power closure for block and full-chip designs.
- Perform physical verification, DRC/LVS/LEC checks and resolve foundry/EDA issues.
- Conduct simulations and analyses to optimize power, performance, and area.
- Design and maintain RTL-to-GDS flows and related backend tool infrastructure.
- Architect and implement large-scale automation frameworks using Shell/Python/Tcl scripting.
- Drive power optimization techniques (DVFS, multi-Vt, power domains, UPF/CPF) and power analysis.
- Integrate AI-driven methods into the physical design flow and evaluate autonomous optimization approaches.
- Interface with foundry and EDA vendors; present technical status and risk assessments to senior management.
- Produce and review detailed technical documentation; mentor and provide guidance to team members.
Requirements
Core technical skills and experience required; education details are summarized separately below.
- Proven ASIC physical design experience at block and full-chip scale (place & route, ECO, STA, timing/power closure, physical verification).
- Hands-on experience with advanced FinFET process nodes and common backend flows (RTL->GDS).
- Strong scripting ability in Shell, Python and Tcl to build automation and flow infrastructure.
- Experience working with foundry processes and EDA toolsets; ability to debug tool/flow issues.
- Ability to lead technical decisions, mentor engineers, and communicate tradeoffs to senior stakeholders.
- Nice-to-have: experience with power optimization techniques (DVFS, multi-Vt, UPF/CPF) and AI/LLM-driven or autonomous-agent approaches applied to EDA challenges.
Education Requirements
Degrees and experience combinations are stated as minimum requirements: Bachelor's degree in Science, Engineering, Computer Science, Electrical/Electronics Engineering or related field (with roughly 3–4+ years of ASIC/physical design experience); OR Master's degree in a related field with fewer years of experience; OR PhD in a related field with fewer years of experience. Preferred fields include VLSI, Electrical/Electronic Engineering, Physics, Computer Engineering, or Computer Science. Equivalent practical experience is acceptable where stated.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
