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SoC Physical Design Engineer, Senior Staff

Qualcomm
September 10, 2026
Full-time
On-site
Bengaluru, Karnataka, India
Physical Design Jobs, Level - Senior

Job Title

SoC Physical Design Engineer, Senior Staff

Role Summary

As a Senior Staff Physical Design Engineer on the hardware engineering team in Bangalore, you will lead physical implementation and sign-off for complex SoC subsystems. The role focuses on floorplan, place-and-route, sign-off convergence, and PPA delivery across advanced process nodes.

Work includes cross-functional integration with IP and verification teams, driving automation to meet power, performance and area targets, and mentoring a small team to deliver project milestones.

Experience Level

Senior-level / Senior Staff. Technical leadership with responsibility for managing small teams and complex subsystems. See Education Requirements for years-of-experience guidance by degree.

Responsibilities

Primary responsibilities include delivering physical design and PPA targets for SoC subsystems and leading implementation activities.

  • Lead Netlist2GDS flow: floorplan, place-and-route, and sign-off convergence.
  • Perform and optimize Static Timing Analysis (STA) and sign-off optimizations.
  • Implement low-power techniques: UPF, multi-voltage domains, and power gating.
  • Integrate IP and manage physical integration across subsystems.
  • Drive automation and scripting to improve PPA and implementation cycle time.
  • Work across multiple advanced process nodes and manage node migration issues.
  • Mentor and manage a small team to meet project schedules and PPA targets.
  • Collaborate with circuit design, verification, and manufacturing teams during bring-up and tapeout.

Requirements

Must-have technical skills and experience to perform the role.

  • Proven expertise in floorplan, place-and-route (PnR), and full Netlist2GDS physical implementation.
  • Strong experience with sign-off convergence and STA-driven optimizations.
  • Practical experience implementing low-power methodologies (UPF, multi-voltage domains, power gating).
  • Solid understanding of ASIC physical design flows, methodologies, circuit design, and device physics in deep sub-micron processes.
  • Hands-on experience across multiple advanced technology nodes, including lower-node support.
  • Ability to develop and apply automation to improve PPA and implementation efficiency.
  • Demonstrated experience leading small teams and delivering complex physical design projects.

Nice-to-have:

  • Experience in product-based companies and large-scale SoC programs.

Education Requirements

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with 6+ years of hardware engineering experience; OR Master's degree in those fields with 5+ years; OR PhD with 4+ years. Preference for candidates from top-tier institutes.


About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.

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Date Posted: 2026-09-10