SOC Physical Design Engineer

Job Title

SOC Physical Design Engineer

Role Summary

Implement and optimize RTL-to-GDSII blocks and subsystems for advanced technology nodes, focusing on placement & routing, timing closure, and sign-off. Work within a hybrid engineering team to ensure high-performance, low-power silicon that integrates into SoC-level designs.

Experience Level

Senior — typically 8+ years with a Bachelor's, 6+ years with a Master's, or 4+ years with a PhD in physical design for advanced nodes.

Responsibilities

Deliver physical implementation and sign-off for complex blocks and subsystems; collaborate across teams to integrate into SoC.

• Perform logic synthesis, floor-planning, placement and routing for designs of ~2–3M instances.
• Conduct timing analysis and optimization to meet high-frequency targets (~2 GHz) at advanced nodes (7nm or below).
• Implement clock tree synthesis (CTS) strategies and perform IR/EM analysis and formal verification for convergence.
• Ensure DRC/LVS cleanliness and prepare GDSII handoff for blocks/subsystems.
• Use Synopsys and Cadence tool flows (e.g., DC, ICC2/Fusion/Innovus, PrimeTime, Calibre/ICV, Conformal/Formality).
• Develop and maintain scripts (Python, TCL, Perl) to automate flows and improve productivity.
• Debug physical design issues, collaborate with cross-functional teams, and drive issues to closure.

Requirements

Must-have technical skills and experience required for the role.

• Proven RTL-to-GDSII implementation experience including PnR, CTS, sign-off flows, and timing closure.
• Hands-on experience with Synopsys and Cadence physical-design tool suites.
• Strong scripting skills for automation (Python, TCL, Perl).
• Experience with IR/EM analysis and formal verification methods.
• Experience delivering high-speed, low-power subsystem or chip-level designs at advanced process nodes.
• Ability to work with evolving RTL and meet project timelines through disciplined execution.
• Good debugging, problem-solving and cross-team collaboration skills.

Nice-to-have:

• Experience leading or mentoring team members and full-chip implementation and integration experience.
• Experience specifically at lower technology nodes and with emerging process flows.

Education Requirements

Minimum: Bachelor's degree in Electrical Engineering, Electronics Engineering, VLSI Design, or related field. The posting also references Master's and PhD as alternative qualifications with reduced experience thresholds (Master's: 6+ years experience required; PhD: 4+ years experience required). No specific certifications were listed.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.