SoC Physical Design Engineer
Meta PlatformsJob Title
SoC Physical Design Engineer
Role Summary
Join Reality Labs Silicon to lead physical implementation of System-on-Chip designs for power- and area-constrained wearable products. You will collaborate with SoC architects, RTL designers, package engineers, verification, and EDA vendors to deliver tapeout-quality designs in advanced process nodes.
Experience Level
Senior - requires significant experience; posting specifies 8+ years of SoC or ASIC physical design experience.
Responsibilities
Deliver full-chip and block-level physical implementation and drive methodology improvements across the flow.
- Lead physical implementation from floorplanning through tapeout: synthesis, placement, CTS, routing, STA, and signoff.
- Define and implement physical design methodologies and flows to meet strict power, performance, and area goals for wearable products.
- Identify and resolve congestion, timing, and power bottlenecks; develop automation and AI-assisted flows to improve throughput and QoR.
- Collaborate with RTL, DV, DFx, package, and verification teams to ensure timing closure, signal/power integrity, testability, and manufacturability.
- Plan and validate chip-level power grid and clock-tree architectures in partnership with package and power-delivery engineers.
- Manage EDA tool engagement, evaluate vendor tools, and drive flow improvements and tool signoff.
Requirements
Must-have technical skills, tools experience, and measurable domain expertise.
- 8+ years of SoC or ASIC physical design experience, with RTL-to-GDSII responsibility at advanced nodes.
- Hands-on implementation experience at 3nm or below: floorplanning, physical synthesis, placement, CTS, routing, STA, and signoff.
- Proven experience with low-power implementation techniques (power gating, voltage islands, UPF, DVFS) and low-power design tradeoffs.
- Strong static timing analysis skills: timing constraints, exceptions, multi-corner/multi-mode, OCV/POCV, and crosstalk considerations.
- Experience with mainstream EDA tools (examples: Fusion Compiler/Genus, ICC2/Innovus, PrimeTime/Tempus, RedHawk/Voltus) or equivalents.
- Proficiency in scripting (TCL, Python, or Perl) and ability to read Verilog netlists/RTL.
- Track record collaborating across RTL, DV, DFx, package, and vendor teams and driving tapeout execution.
Education Requirements
Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field is listed as required or equivalent practical experience; preferred qualifications include a Master’s or PhD in Electrical Engineering or Computer Engineering. The posting explicitly allows equivalent practical experience in lieu of a degree.
About the Company
Company: Meta Platforms
Headquarters: Menlo Park, California, United States
American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.
