SoC PD Engineer

Job Title

SoC PD Engineer

Role Summary

Senior-level physical design engineer responsible for block-, die-, and chip-level physical implementation on advanced FinFET nodes. The role owns backend design methodology, drives automation and Agentic AI integration in the PD flow, and collaborates with cross-functional teams, foundries, and EDA vendors.

Experience Level

Senior (Staff / Sr. Staff) level. Experience guidance in the posting varies by degree; typical ranges include roughly 4–6+ years of relevant ASIC/hardware engineering experience depending on highest degree held.

Responsibilities

Lead and execute complex SoC physical implementation activities and provide technical leadership across teams.

• Define, model, implement and optimize IP and SoC physical design (place & route, ECO, timing and power closure).
• Lead floor-planning, block and full-chip implementation, and advanced design-rule execution.
• Perform complex simulations and analyses to meet power, performance, and area targets.
• Drive physical verification and signoff activities, including LEC/timing and power closure.
• Develop and maintain RTL-to-GDS flow and backend automation infrastructure.
• Interface with foundry, EDA vendors, and senior management; present methodology and risk assessments for tape-out readiness.
• Mentor and provide guidance to engineering team members; work independently with minimal supervision.

Requirements

Core technical skills and experience required or strongly preferred. Education degree details appear separately below.

• Proven ASIC physical design experience: ECO, STA, physical verification, and power analysis.
• Deep expertise in floor-planning, place & route, timing closure, and physical verification at block and full-chip levels.
• Experience with power-optimization techniques (DVFS, multi-Vt, power domains) and UPF/CPF flows.
• Advanced scripting skills (Shell, Python, Tcl) for architecting large-scale SOC backend automation and flow infrastructure.
• Familiarity with RTL-to-GDS flows and EDA toolchains; ability to write and review detailed technical documentation.
• Experience engaging with foundry and EDA vendors; strong written and verbal communication skills to present to senior stakeholders.
• Preferred: demonstrated experience or vision for applying Agentic AI / LLM-based methods to EDA challenges (autonomous agents, AI-driven optimization, LLM-assisted debugging).

Education Requirements

Posting references Bachelor's, Master’s, or PhD in Science or Engineering fields (examples: VLSI, Electrical/Electronic Engineering, Computer Engineering, Computer Science, Physics) and includes degree-based experience guidelines. The posting also allows equivalent practical work experience in lieu of the listed degrees.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.