SOC Micro-Architect and RTL Designer
MatXJob Title
SOC Micro-Architect and RTL Designer
Role Summary
Design and deliver micro-architecture and RTL for subsystems and chip-level blocks in high-performance SOCs. Work across architecture, RTL, verification, DFT, and physical design to drive designs from specification to sign-off.
This role supports MatX's silicon for large-scale ML/GenAI compute; candidates will own subsystem deliverables and drive area, timing, and functional closure.
Experience Level
Mid-level (Level - Mid-Career). The posting indicates 2+ years of hands-on experience with RTL and related design flows; more experienced candidates are considered for higher responsibility.
Responsibilities
Primary responsibilities include subsystem- and chip-level micro-architecture and RTL design, delivery, and reviews.
- Define and refine micro-architecture and RTL specifications for blocks/subsystems.
- Own design deliverables from architecture through sign-off-ready implementation.
- Plan and drive intermediate and sign-off reviews; track execution, area, and timing closure to meet milestones (design freeze, tapeout).
- Collaborate closely with verification, DFT, and physical design owners to meet performance, power, area, and test-coverage goals.
- Support synthesis, equivalence checking, lint, CDC signoff flows and work with teams to achieve high-quality sign-off.
Requirements
Must-have technical skills and constraints; nice-to-have items listed separately.
- Concept-to-silicon experience delivering ASIC/SOC subsystems or top-level functions from architecture to production silicon.
- 2+ years of hands-on experience with SystemVerilog and scripting/programming languages such as Python and C/C++.
- Production-proven experience with micro-architecture and design concepts for high-performance compute, high-speed connectivity, memory management, or similar functions.
- Experience working with verification teams toward functional and performance coverage closure.
- Hands-on experience with synthesis, equivalence checking, design lint, and clock-domain-crossing practices to achieve sign-off quality.
- Working knowledge of DFT and physical design concepts and methodologies to achieve test coverage and PA/Timing/Power targets.
- This is a hybrid role requiring on-site work in Mountain View, CA three days per week (Tuesday–Thursday).
Nice-to-have:
- Experience with verification, emulation platforms, silicon debug, and bring-up.
- Hands-on experience with PCIe, HBM, DMA, or die-to-die implementations.
Education Requirements
Not specified.
About the Company
Company: MatX
Headquarters: Mountain View, California, USA
MatX specializes in creating faster chips for large language models (LLMs), focusing on innovative hardware and software solutions. The company fosters a collaborative and supportive work environment, welcoming candidates of all experience levels. Their approach prioritizes deep understanding and consideration of novel methods to drive efficiency and performance in their projects, particularly in silicon design and related engineering roles.
