SOC Micro-Architect and RTL Designer
MatXJob Title
SOC Micro-Architect and RTL Designer
Role Summary
Join MatX's Hardware team to design high-performance silicon for ML/AGI workloads. The role spans micro-architecture through sign-off for subsystems and full-chip designs, with focus areas including compute, memory management, and high-speed connectivity.
Work across architecture, RTL, verification, DFT, and physical design teams to meet area, timing, power, and quality goals for production silicon.
Experience Level
Mid-level — typically 5+ years of relevant silicon design experience.
Responsibilities
Primary responsibilities include leading micro-architecture and RTL efforts for subsystems or chip-level functions and driving them to production readiness.
- Contribute to and scale architecture-to-design methodology across blocks, subsystems, and full-chip flows.
- Own subsystem or chip-level deliverables from micro-architecture to sign-off-ready RTL.
- Plan and lead micro-architecture and design reviews; track progress toward design freeze and tapeout milestones.
- Collaborate closely with verification, DFT, and physical design teams to achieve performance, power, area, and timing targets.
Requirements
Core technical and logistical requirements for the role.
Must-have:- Concept-to-silicon experience delivering ASIC/SOC subsystems or top-level functions from architecture to production silicon.
- 5+ years working with SystemVerilog, Python, and C/C++ for chip design and automation.
- Production-proven micro-architecture and RTL design experience for high-performance compute, memory management, or high-speed connectivity.
- Experience testing designs and collaborating with verification teams to meet performance and coverage goals.
- Hands-on experience with synthesis, equivalence checking, design lint, clock-domain crossing analysis, and related sign-off flows.
- Knowledge of DFT and physical design concepts to achieve high test coverage and timing/power/area objectives.
- Ability to work on-site in Mountain View, CA three days per week (Tuesday–Thursday) and authorization to work in the United States.
- Familiarity with verification/emulation platforms and methodologies.
- Experience with silicon debug and bring-up.
- Hands-on experience with PCIe, HBM, DMA, or die-to-die subsystems and firmware/silicon implementations.
Education Requirements
Not specified.
About the Company
Company: MatX
Headquarters: Mountain View, California, USA
MatX specializes in creating faster chips for large language models (LLMs), focusing on innovative hardware and software solutions. The company fosters a collaborative and supportive work environment, welcoming candidates of all experience levels. Their approach prioritizes deep understanding and consideration of novel methods to drive efficiency and performance in their projects, particularly in silicon design and related engineering roles.
