SoC/IP Design Verification Engineer

Job Title

SoC/IP Design Verification Engineer

Role Summary

Hands-on verification engineer responsible for planning, implementing, and executing verification for complex SoC and IP blocks. The role covers UVM testbench development, test content creation, coverage closure, and debug across block, subsystem, and SoC levels.

Works closely with RTL design, architecture, firmware, and validation teams to ensure features are verified and silicon quality targets are met on schedule.

Experience Level

Mid-level - typically requires 5+ years of relevant SoC/IP design verification experience.

Responsibilities

Primary responsibilities include ownership of verification lifecycle, environment implementation, test development, and cross-functional collaboration.

• Own verification lifecycle for one or more IPs/subsystems/SoC features: requirements decomposition, test plan, coverage strategy, execution, and signoff.
• Architect and implement UVM environments: agents, drivers, monitors, sequencers, scoreboards, and reusable components.
• Develop test content: constrained-random sequences, scenario tests, stimulus libraries, checkers, and assertions.
• Debug failures across simulation and emulation using waveforms, logs, assertions, and reference-model comparisons.
• Drive functional and code coverage closure: define metrics, analyze gaps, and implement closure strategies.
• Integrate and customize VIPs (AXI/ACE/PCIe/DDR etc.) and coordinate with IP teams for models and coverage.
• Leverage SVA and formal methods where appropriate to improve verification quality.
• Contribute to verification infrastructure, regressions, CI/CD, and automation (Makefiles, Python, farm scripts).
• Document verification plans, results, risks, and present signoff evidence to stakeholders.

Requirements

Minimum and preferred technical qualifications and attributes for initial consideration.

• Must-have: 5+ years of SoC/IP design verification experience with strong UVM/SystemVerilog skills (testbenches, agents, scoreboards, virtual sequences, factory/objection/callback mechanisms).
• Proven debug skills in simulation/emulation (examples: Synopsys VCS, Cadence Xcelium, Siemens Questa; waveform tools such as Verdi/DVE/SimVision).
• Experience with coverage-driven verification: functional coverage modeling, code coverage analysis, and closure workflows.
• Scripting proficiency for automation and regressions (Python, Shell, Make/CMake).
• Advanced English communication skills.
• Must have unrestricted, permanent right to work in Mexico; this role is not eligible for visa or immigration sponsorship.
• Nice-to-have: SoC-level verification (fabric/interconnect, security), experience with standard protocols (AXI/ACE/CHI, PCIe, DDR, USB, MIPI, I3C, SPI/I2C, Ethernet), assertion-based verification and formal tools, power-aware verification (UPF/CPF), emulation/prototyping experience, performance/throughput test development, C/C++/SystemC reference models, and experience leading small teams or driving tapeout signoff.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. (Degree stated as a minimum qualification in the source.)

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.