SoC/IP Design Verification Engineer

Job Title

SoC/IP Design Verification Engineer

Role Summary

Responsible for owning and executing the verification lifecycle for SoC/IP blocks, from requirements decomposition and test planning through testbench development, coverage closure, and signoff.

Work with RTL design, architecture, firmware, and validation teams to deliver robust verification environments and high-quality silicon on schedule.

Experience Level

Mid-level — typically requires 5+ years of SoC/IP design verification experience.

Responsibilities

Primary verification duties and delivery expectations:

• Define verification plans, coverage strategy, and signoff criteria for IPs, subsystems, or SoC features.
• Architect and implement UVM-based testbenches (agents, drivers, monitors, sequencers, scoreboards, reference models).
• Develop directed and constrained-random test content, stimulus libraries, checkers, and assertions.
• Execute regressions in simulation and emulation; debug failures via waveforms, logs, assertions, and model comparisons.
• Drive functional and code coverage closure and implement strategies to close coverage holes.
• Integrate VIPs (AXI/ACE/PCIe/DDR etc.) and collaborate with internal/external IP teams for models and checkers.
• Improve verification flows, CI/CD, regressions, and automation infrastructure (Makefiles, Python utilities, farm scripts).
• Document verification plans, present status/risks, and provide signoff evidence to stakeholders.

Requirements

Must-have skills and qualifications (concise):

• 5+ years of SoC/IP design verification experience, including test planning and coverage-driven verification.
• UVM/SystemVerilog expertise for testbenches, virtual sequences, factories, and callbacks.
• Proven debug experience in simulation/emulation (examples: Synopsys VCS, Cadence Xcelium, Siemens Questa; waveform tools like Verdi/DVE/SimVision).
• Functional coverage modeling, code coverage analysis, and coverage-closure workflows.
• Scripting for automation and regressions (Python, Shell, Make/CMake).
• Advanced English communication skills for technical collaboration and reporting.
• Must have unrestricted, permanent right to work in Mexico; this role is not eligible for visa or immigration sponsorship.

Preferred (nice-to-have):

• SoC-level verification (fabric/interconnect, security) and experience integrating standard protocols (AXI/ACE/CHI, PCIe, DDR, USB, MIPI, I3C, SPI/I2C, Ethernet).
• Assertion-based verification (SVA) and formal tools (e.g., JasperGold) experience.
• Power-aware verification (UPF/CPF), multi-voltage domains, and retention/isolation strategies.
• Emulation/FPGA prototyping (Palladium, Zebu, Veloce), transaction-level acceleration and hybrid verification experience.
• Performance/latency/throughput test development and reference-model/scoreboard design; exposure to C/C++/SystemC or firmware-aware verification.
• Experience leading small teams, mentoring engineers, or driving signoff for tapeout.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field (as listed in the posting).

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.