SOC Integration Engineer

Job Title

SOC Integration Engineer

Role Summary

Responsible for integrating subsystem RTL into a full-chip SoC top-level design, building automation for SOC RTL generation, and coordinating with architecture, physical design, package, and board teams to meet connectivity and timing requirements.

Position is based in Mountain View with an in-office cadence (Tuesdays–Thursdays); the role partners closely with subsystem owners, full-chip owners, and cross-functional teams.

Experience Level

Mid-level. Years of experience not explicitly stated; role expects prior SOC integration and RTL/physical-design collaboration experience.

Responsibilities

Key responsibilities include:

• Engineer SOC top-level RTL and integration methodology to combine subsystem RTL into a full-chip design.
• Partner with subsystem owners to facilitate block integration and lead development of SOC top-level RTL.
• Implement and maintain automation for SOC RTL generation and build processes to enable on-the-fly top-level RTL creation.
• Collaborate with physical design to incorporate RTL modules, feedthroughs, and highways that align with floorplan connectivity.
• Establish clock and reset methodologies across domains through cross-functional coordination.
• Define SoC-level timing constraints and validate them against subsystem and physical design requirements.
• Provide technical input to package and board teams, including SOC pin definitions and interposer netlist support.

Requirements

Must-have and preferred skills:

• Must-have: Proficiency in SystemVerilog and scripting (Python or Perl).
• Proven experience integrating high-performance compute elements (CPUs, GPUs, accelerators) and high-speed interconnects (e.g., UCIE) within SOC RTL.
• Working knowledge of logical equivalency verification for SOC-level interfaces and ability to work with physical design on floorplan requirements.
• Experience generating memory wrappers and integrating DFT wrappers into subsystem RTL.
• Hands-on experience with synthesis, linting, CDC (clock & reset-domain-crossing) verification, and timing constraint validation toward SOC sign-off.
• Nice-to-have: Familiarity with emulation platforms, verification methodologies, and using AI-driven tools to automate SOC integration tasks.

Education Requirements

No specific degree or field of study is listed. Compensation and level consideration reference relevant education and training but do not mandate a particular credential.

About the Company

Company: MatX

Headquarters: Mountain View, California, USA

MatX specializes in creating faster chips for large language models (LLMs), focusing on innovative hardware and software solutions. The company fosters a collaborative and supportive work environment, welcoming candidates of all experience levels. Their approach prioritizes deep understanding and consideration of novel methods to drive efficiency and performance in their projects, particularly in silicon design and related engineering roles.