SOC Integration Engineer

Job Title

SOC Integration Engineer

Role Summary

Join the Hardware team to design and automate SoC top-level RTL integration, coordinating subsystem owners and physical design to deliver a complete, manufacturable system-on-chip. The role focuses on engineering scalable RTL integration flows, automation for top-level generation, and ensuring timing, clock/reset, and floorplan alignment across teams.

Experience Level

Mid-level. Years of experience not specified.

Responsibilities

You will own SOC top-level RTL integration and automation, working across architecture, design, verification, and physical teams.

• Drive evolution of architecture-to-design methodology for SOC-top RTL integration.
• Partner with subsystem owners to integrate blocks and develop SOC top-level RTL.
• Implement automation for SOC top-level RTL generation and build processes.
• Coordinate with Physical Design to incorporate RTL modules, feedthroughs, and chip-level floorplan connectivity.
• Establish and enforce clocking and reset methodologies across domains.
• Define SOC-level timing constraints and validate them against subsystem and physical design requirements.
• Define SOC pin requirements and support package/board teams with interposer/netlist generation.

Requirements

Concise list of required and desirable skills. Must-have items are first.

• Must-have: Proficiency in SystemVerilog and scripting (Python or Perl) for RTL and flow automation.
• Must-have: Experience integrating high-performance compute elements (CPUs, GPUs, accelerators) and high-speed interconnects (experience with UCIE or similar).
• Must-have: Practical knowledge of logical equivalency verification for SOC-level interfaces and collaboration with physical design on floorplan constraints.
• Must-have: Experience generating memory wrappers and integrating DFT wrappers into subsystem RTL.
• Must-have: Experience with design synthesis, linting, clock- and reset-domain crossing (CDC) analysis, and timing constraint validation to achieve SOC sign-off.
• Must-have: Authorization to work in the United States and ability to work on-site in Mountain View Tuesdays–Thursdays; role requires compliance with U.S. export control restrictions.
• Nice-to-have: Familiarity with emulation platforms and advanced verification methodologies.
• Nice-to-have: Experience applying AI-driven tools to architect automation for SOC integration.

Education Requirements

Not specified.

About the Company

Company: MatX

Headquarters: Mountain View, California, USA

MatX specializes in creating faster chips for large language models (LLMs), focusing on innovative hardware and software solutions. The company fosters a collaborative and supportive work environment, welcoming candidates of all experience levels. Their approach prioritizes deep understanding and consideration of novel methods to drive efficiency and performance in their projects, particularly in silicon design and related engineering roles.