SoC Front-End Integrator, Senior to Staff

Job Title

SoC Front-End Integrator — Senior to Staff

Role Summary

Join the SoC design team to integrate RTL/IP blocks, manage chip-level interconnect and subsystem interfaces, and ensure correct operation from pre-silicon verification through post-silicon validation. The role emphasizes timing closure, reliable cross-domain synchronization, and cross-team coordination within complex SoC platforms.

Experience Level

Senior level. The posting expects experienced engineers (see Education Requirements for degree-based experience alternatives); one section lists 5+ years in SoC front-end integration as a typical expectation.

Responsibilities

Primary responsibilities include:

• Integrate RTL and internal IP blocks into SoC designs.
• Ensure efficient communication and data flow between subsystems (CPU, memory, interconnect, peripherals).
• Design and optimize bus/interconnect implementations (AXI, AHB, APB).
• Manage clock/reset domain crossing (CDC/RDC) and synchronization across domains.
• Collaborate with verification teams to validate subsystem interactions and coverage.
• Work with physical design teams to achieve timing closure and integration readiness.
• Debug and resolve integration issues across simulation, emulation, and silicon validation.
• Support system-level bring-up and post-silicon performance correlation.
• Drive methodology improvements and automation for the SoC integration flow.
• Provide guidance on interface protocols, integration best practices, and coding styles.

Requirements

Core technical skills and experience required and preferred.

• Must-have: Hands-on SoC front-end integration experience (senior-level; see Education Requirements for degree/experience combinations).
• Proficiency in Verilog/SystemVerilog and SoC integration methodologies.
• Strong understanding of chip-level communication protocols and subsystem interaction.
• Familiarity with RTL-to-GDSII flow and timing closure processes.
• Strong scripting skills (Python, Tcl, or Shell).
• Proven problem-solving skills and effective cross-functional communication.
• Willingness to travel occasionally across APAC and other regions.

Preferred:

• Experience with low-power design techniques and clock/power domain crossing.
• Deep knowledge of AMBA protocols (AXI, AHB, APB) and interconnect design.
• Familiarity with post-silicon validation and subsystem debug.
• Exposure to EDA tools such as Synopsys Design Compiler, VCS, or Cadence tools.
• Experience correlating pre-silicon verification with post-silicon performance and yield.

Education Requirements

Degrees accepted: Bachelor's, Master’s, or PhD in Electrical Engineering, Computer Engineering, Science, Engineering, or a related technical field. The posting includes multiple alternative minimums: either a Bachelor's degree plus 4+ years of relevant ASIC/design/verification/integration/validation experience, or a Master’s degree plus 3+ years, or a PhD plus 2+ years. One section also lists a Master’s in EE/CE with 5+ years of hands-on SoC front-end integration experience.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.