SoC Engineering Staff Engineer

Job Title

SoC Engineering Staff Engineer

Role Summary

Individual contributor role owning full RTL-to-GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm). Work within a global physical-design team to deliver tape-outs, focusing on synthesis, place-and-route, timing closure, and physical verification.

The role emphasizes hands-on technical execution, automation of flows, collaboration with cross-functional teams, and mentoring junior engineers.

Experience Level

Senior — 8+ years of relevant physical-design experience, with strong background in advanced nodes (7nm/5nm/3nm).

Responsibilities

Key responsibilities include ownership of physical design implementation and delivery of high-quality silicon.

• Independently own full RTL2GDSII implementation for advanced process nodes and ensure successful tape-outs.
• Perform synthesis, place & route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA).
• Execute block-level and full-chip floor-planning, timing closure, EMIR analysis, and physical verification.
• Collaborate with cross-functional and geographically distributed teams to resolve design issues and meet schedules.
• Use and optimize Synopsys EDA tools (Design Compiler, IC Compiler II, PrimeTime) for design implementation.
• Develop and maintain automation scripts (Python, PERL, TCL or similar) to improve design flow efficiency.
• Contribute to methodology improvements and mentor junior engineers when needed.

Requirements

Must-have technical skills and experience.

• 8+ years of hands-on physical-design experience at advanced nodes (7nm/5nm/3nm).
• Proven experience with RTL2GDSII flows: synthesis, P&R, CTS, timing optimization, STA, EMIR, and physical verification.
• Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime.
• Strong scripting and automation skills (Python, PERL, TCL, or similar).
• Solid understanding of timing constraints, timing closure techniques, and floor-planning for block and full-chip designs.
• Experience with high-frequency and low-power design methodologies.

Nice-to-have

• Prior ownership of full-chip tape-outs and first-pass silicon success.
• Experience improving or defining physical-design methodologies and tooling workflows.

Education Requirements

Bachelor's or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related technical field; or equivalent practical experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.