SoC Engineering Staff Engineer
Senior physical design engineer responsible for RTL-to-GDSII implementation and signoff of UCIE IP. Work within an IP/SoC engineering team to floorplan, place-and-route, close timing, and complete signoff for advanced-node designs.
Primary mission: deliver high-quality, tape-out-ready IP by improving flows, integrating complex macros and third-party blocks, and automating repeatable tasks.
Senior-level. The posting requests 5+ years of hands-on block-level physical design experience, including exposure to advanced nodes (7nm or below).
Core responsibilities include ownership of the physical implementation flow and collaboration across architecture, RTL, and circuit teams.
Must-have technical skills and experience.
Not specified.
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
