SoC Engineering Senior Staff Engineer

Job Title

SoC Engineering Senior Staff Engineer

Role Summary

Senior physical-design engineer responsible for implementing DDR and HBM PHY IP from RTL through physical implementation, timing closure, and signoff on advanced FinFet nodes. The role leads customer-facing design engagements within the DDR and HBM PHY hardening service line and coordinates across Synopsys internal teams and external customer teams.

Experience Level

Senior - requires senior-level experience. The posting requests 5+ years of hands-on ASIC physical-design experience and multiple successful tapeouts on advanced nodes.

Responsibilities

Core responsibilities include taking PHY designs to production and leading technical execution on customer projects.

• Implement DDR and HBM PHYs for customer ASICs/SOCs from RTL through physical implementation and signoff.
• Run synthesis, place-and-route, and physical verification using ICC2, Fusion Compiler, and ICV.
• Perform DFT insertion and ATPG to ensure manufacturable, testable designs.
• Serve as technical lead on engagements, coordinating internal and customer teams to meet schedules.
• Debug timing, power, and physical-design issues across multi-million-gate designs under tight tapeout timelines.
• Provide regular technical status, risk assessments, and mitigation plans to management and customers.
• Mentor and guide junior engineers on methodology and tool usage for closure on advanced nodes.

Requirements

Must-have technical skills and proven experience; listed separately are strong pluses.

• Must-have: 5+ years in ASIC physical design with multiple tapeouts on advanced nodes.
• Must-have: Deep working knowledge of Synopsys tools: Design Compiler, PrimeTime, ICC2 or Fusion Compiler, and ICV.
• Must-have: Experience closing timing, power, and signal-integrity issues on complex high-speed interfaces.
• Must-have: Strong debugging skills across the physical-design flow from synthesis through signoff.
• Must-have: Experience with FinFet process technologies (7nm, 5nm, or below).
• Nice-to-have: Direct experience implementing DDR or HBM PHY designs.
• Nice-to-have: Familiarity with DFT methodologies and ATPG tools.

Education Requirements

Not specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.