SoC Engineering Senior Engineer

Job Title

SoC Engineering Senior Engineer

Role Summary

Lead synthesis and timing-closure activities for SoC blocks, subsystems, or full chips, working from RTL handoff through timing signoff. Collaborate with RTL, DFT, and physical implementation teams to resolve timing, clocking, and low-power issues.

Focus on multi-mode, multi-corner constraint development, automation, and verifying deliverables to enable timely tapeouts.

Experience Level

Senior — employer guidance lists 0–5+ years of hands-on experience in digital design, timing closure, or SoC implementation.

Responsibilities

Accountabilities include owning timing flow, developing constraints, validating deliverables, and building automation to scale timing closure across designs.

• Own synthesis and timing closure from RTL handoff through timing signoff for blocks, subsystems, or SoCs.
• Develop, validate, and debug SDC timing constraints for multi-mode, multi-corner scenarios across complex clocking architectures.
• Perform deliverable sanity checks: constraints analysis, LDRC, logical equivalence checking, and low-power verification at RTL and netlist levels.
• Work directly with RTL, DFT, and physical implementation teams to resolve violations, optimize paths, and meet performance targets.
• Lead timing-related technical discussions and translate design goals into actionable timing strategies.
• Automate checks, flows, and reporting using TCL, Perl, or Python to improve efficiency and reduce manual errors.
• Debug timing issues using Synopsys Fusion Compiler and PrimeTime; analyze timing paths, clock skew, and setup/hold violations.

Requirements

Must-have:

• Proven experience performing multi-mode, multi-corner timing closure of complex blocks, subsystems, or SoCs from synthesis through timing signoff.
• Strong expertise in SDC constraint development, validation, and debugging for various modes and corners.
• Proficiency with Synopsys Fusion Compiler and PrimeTime for synthesis, timing analysis, and signoff.
• Solid scripting skills in TCL, Perl, or Python for automation and flow development.
• Experience with low-power concepts (UPF) and performing low-power checks at RTL and netlist levels.
• Experience with logical equivalence checking and formal verification tools.
• Ability to diagnose complex timing reports and prioritize root causes under schedule pressure.

Nice-to-have:

• Experience leading timing closure across multiple blocks or full-SoC projects and mentoring others on timing strategy.
• Prior work on designs with complex clocking and multiple power domains for high-performance SoCs.

Education Requirements

Bachelor's or Master's degree in IC Design, Semiconductor Engineering, Electrical Engineering, or a related technical field (as stated by the employer).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.