SoC Engineering Architect
SynopsysJob Title
SoC Engineering Architect
Role Summary
Lead the definition and delivery of SoC subsystems by translating product requirements into implementable subsystem architectures. You will work on memory controllers, interconnect clusters, compute blocks, power management units, and communication subsystems for Synopsys Digital IP Subsystems.
Work closely with IP designers, SoC architects, verification, firmware/software, and physical design teams to ensure subsystem feasibility, interoperability, and production readiness.
Experience Level
Senior - typically 15+ years of semiconductor industry experience with 10+ years in semiconductor design, IP integration, or SoC/subsystem architecture roles.
Responsibilities
Responsible for architecture, integration, validation, and documentation of IP subsystems.
- Define subsystem architectures that balance performance, power, area, security, and functionality.
- Integrate multiple IP blocks into cohesive subsystems; ensure interface compatibility and dataflow alignment with SoC interconnects and firmware needs.
- Lead architecture exploration, IP selection, subsystem modeling, and validation using simulation and analysis tools.
- Coordinate across SoC architects, verification, software/firmware, and physical design to ensure feasibility and correctness.
- Specify verification requirements for functionality, corner cases, power states, and protocol compatibility and work with DV teams to achieve coverage.
- Produce architecture documents, subsystem specifications, and engineering guidelines for technical and non-technical stakeholders.
- Participate in silicon bring-up, debug sessions, and subsystem-level performance characterization.
Requirements
Must-have technical skills and experience; concise list of required competencies followed by a few desirable skills.
- 10+ years in semiconductor design, IP integration, or SoC/subsystem architecture with a proven record of delivering complex subsystems.
- Deep, hands-on expertise in Verilog and SystemVerilog for RTL design and simulation; experience with industry-standard simulation tools.
- Strong working knowledge of interface protocols such as AMBA APB, AXI, CHI, DDR, PCIe, Ethernet, USB, or UFS, including protocol-level debugging and performance analysis.
- Experience with synthesis flows, lint, CDC analysis, low-power design methodologies, and verification closure using SystemVerilog UVM and BFM/test environment development.
- Proven ability to coordinate cross-disciplinary teams (hardware, firmware, software, verification, physical design) to drive projects to completion.
- Excellent technical writing and communication skills; ability to produce clear architecture documents and specifications.
- Practical experience in silicon bring-up, debug, or subsystem performance characterization is desirable.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. The posting specifies 15+ years of overall semiconductor experience alongside these degree expectations.
More about the team: Synopsys IP Subsystems
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
