SoC Engineer (Synthesis/Timing)

Job Title

SoC Engineer (Synthesis/Timing)

Role Summary

Member of an SoC engineering team responsible for RTL-to-GDS flow tasks focused on logic synthesis and static timing analysis (STA). Works with digital design, place-and-route, and verification teams to achieve timing closure and manufacturable netlists for ASIC/SoC projects.

Experience Level

Mid-level. The posting does not specify years; typical hires for this title have roughly 3–7 years of relevant SoC/ASIC synthesis and timing experience.

Responsibilities

Primary responsibilities expected for this role:

• Develop and run synthesis flows to convert RTL to gate-level netlists while meeting area, timing, and power targets.
• Create and maintain timing constraints and SDC files; perform static timing analysis and identify critical paths.
• Analyze and debug timing violations; propose and implement RTL or constraint fixes to close timing.
• Integrate synthesis results with place-and-route teams and validate timing across tool flows.
• Automate recurring tasks and flows using scripting (TCL/Python/Perl) and maintain runbooks.
• Participate in design reviews, provide sign-off recommendations, and document results and issues.
• Collaborate with verification, architecture, and P&R engineers to meet project milestones.

Requirements

Essential and preferred skills for the role.

• Must-have:
  • Practical experience with logic synthesis and static timing analysis in ASIC/SoC projects.
  • Familiarity with common synthesis/STA practices: constraints (SDC), timing exception handling, and timing closure strategies.
  • Scripting skills for flow automation (TCL, Python, or similar).
  • Ability to read and analyze RTL and gate-level netlists to diagnose timing issues.
  • Strong collaboration and communication skills to work across P&R, verification, and architecture teams.
• Nice-to-have:
  • Experience with Synopsys tools such as Design Compiler and PrimeTime or equivalent commercial tools.
  • Prior work on complex SoC blocks, low-power design techniques, or physical implementation interactions.
  • Knowledge of sign-off criteria and manufacturing-aware design practices.

Education Requirements

Not specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.